[clang] 32a9c09 - [clang][CodeGen] Regenerate tests checks after 94795a37e892cfedb570c70a5101ea88348e60c7

Simon Pilgrim via cfe-commits cfe-commits at lists.llvm.org
Fri Oct 6 05:27:50 PDT 2023 

Author: Simon Pilgrim
Date: 2023-10-06T13:27:31+01:00
New Revision: 32a9c096091081736480250da66a2702375a6210

URL: https://github.com/llvm/llvm-project/commit/32a9c096091081736480250da66a2702375a6210
DIFF: https://github.com/llvm/llvm-project/commit/32a9c096091081736480250da66a2702375a6210.diff

LOG: [clang][CodeGen] Regenerate tests checks after 94795a37e892cfedb570c70a5101ea88348e60c7

These were missed as I didn't expect clang codegen to be updated

Added: 
    

Modified: 
    clang/test/CodeGen/X86/avx-shuffle-builtins.c
    clang/test/CodeGen/aarch64-neon-vcmla.c

Removed: 
    


################################################################################
diff  --git a/clang/test/CodeGen/X86/avx-shuffle-builtins.c b/clang/test/CodeGen/X86/avx-shuffle-builtins.c
index 9917598f6eb15c2..9109247e534f4f0 100644
--- a/clang/test/CodeGen/X86/avx-shuffle-builtins.c
+++ b/clang/test/CodeGen/X86/avx-shuffle-builtins.c
@@ -1,5 +1,5 @@
-// RUN: %clang_cc1 -ffreestanding %s -O3 -triple=x86_64-apple-darwin -target-feature +avx -emit-llvm -o - | FileCheck %s
-// RUN: %clang_cc1 -ffreestanding %s -O3 -triple=i386-apple-darwin -target-feature +avx -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -ffreestanding %s -O3 -triple=x86_64-apple-darwin -target-feature +avx -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,X64
+// RUN: %clang_cc1 -ffreestanding %s -O3 -triple=i386-apple-darwin -target-feature +avx -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,X86
 // FIXME: This is testing optimized generation of shuffle instructions and should be fixed.
 
 
@@ -129,8 +129,11 @@ __m256i test_mm256_insertf128_si256_1(__m256i a, __m128i b) {
 // Make sure we have the correct mask for each extractf128 case.
 
 __m128 test_mm256_extractf128_ps_0(__m256 a) {
-  // CHECK-LABEL: test_mm256_extractf128_ps_0
-  // CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3>
+  // X64-LABEL: test_mm256_extractf128_ps_0
+  // X64: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3>
+  //
+  // X86-LABEL: test_mm256_extractf128_ps_0
+  // X86: shufflevector{{.*}}<i32 0, i32 1>
   return _mm256_extractf128_ps(a, 0);
 }
 
@@ -142,13 +145,16 @@ __m128d test_mm256_extractf128_pd_0(__m256d a) {
 
 __m128i test_mm256_extractf128_si256_0(__m256i a) {
   // CHECK-LABEL: test_mm256_extractf128_si256_0
-  // CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3>
+  // CHECK: shufflevector{{.*}}<i32 0, i32 1>
   return _mm256_extractf128_si256(a, 0);
 }
 
 __m128 test_mm256_extractf128_ps_1(__m256 a) {
-  // CHECK-LABEL: test_mm256_extractf128_ps_1
-  // CHECK: shufflevector{{.*}}<i32 4, i32 5, i32 6, i32 7>
+  // X64-LABEL: test_mm256_extractf128_ps_1
+  // X64: shufflevector{{.*}}<i32 4, i32 5, i32 6, i32 7>
+  //
+  // X86-LABEL: test_mm256_extractf128_ps_1
+  // X86: shufflevector{{.*}}<i32 2, i32 3>
   return _mm256_extractf128_ps(a, 1);
 }
 
@@ -160,7 +166,7 @@ __m128d test_mm256_extractf128_pd_1(__m256d a) {
 
 __m128i test_mm256_extractf128_si256_1(__m256i a) {
   // CHECK-LABEL: test_mm256_extractf128_si256_1
-  // CHECK: shufflevector{{.*}}<i32 4, i32 5, i32 6, i32 7>
+  // CHECK: shufflevector{{.*}}<i32 2, i32 3>
   return _mm256_extractf128_si256(a, 1);
 }
 

diff  --git a/clang/test/CodeGen/aarch64-neon-vcmla.c b/clang/test/CodeGen/aarch64-neon-vcmla.c
index 59ac17a24cccf75..9cd046d63d1b520 100644
--- a/clang/test/CodeGen/aarch64-neon-vcmla.c
+++ b/clang/test/CodeGen/aarch64-neon-vcmla.c
@@ -167,10 +167,8 @@ float16x4_t test_vcmla_laneq_f16(float16x4_t acc, float16x4_t lhs, float16x8_t r
 }
 
 // CHECK-LABEL: @test_vcmlaq_lane_f16(
-// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
-// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
-// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
-// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
+// CHECK: [[DUP:%.*]] = shufflevector <4 x half> %rhs, <4 x half> poison, <8 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3> 
+// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP]])
 // CHECK: ret <8 x half> [[RES]]
 float16x8_t test_vcmlaq_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
   return vcmlaq_lane_f16(acc, lhs, rhs, 1);
@@ -243,10 +241,8 @@ float16x4_t test_vcmla_rot90_laneq_f16(float16x4_t acc, float16x4_t lhs, float16
 }
 
 // CHECK-LABEL: @test_vcmlaq_rot90_lane_f16(
-// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
-// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
-// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
-// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot90.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
+// CHECK: [[DUP:%.*]] = shufflevector <4 x half> %rhs, <4 x half> poison, <8 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
+// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot90.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP]])
 // CHECK: ret <8 x half> [[RES]]
 float16x8_t test_vcmlaq_rot90_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
   return vcmlaq_rot90_lane_f16(acc, lhs, rhs, 1);
@@ -319,10 +315,8 @@ float16x4_t test_vcmla_rot180_laneq_f16(float16x4_t acc, float16x4_t lhs, float1
 }
 
 // CHECK-LABEL: @test_vcmlaq_rot180_lane_f16(
-// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
-// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
-// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
-// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot180.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
+// CHECK: [[DUP:%.*]] = shufflevector <4 x half> %rhs, <4 x half> poison, <8 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
+// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot180.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP]])
 // CHECK: ret <8 x half> [[RES]]
 float16x8_t test_vcmlaq_rot180_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
   return vcmlaq_rot180_lane_f16(acc, lhs, rhs, 1);
@@ -395,10 +389,8 @@ float16x4_t test_vcmla_rot270_laneq_f16(float16x4_t acc, float16x4_t lhs, float1
 }
 
 // CHECK-LABEL: @test_vcmlaq_rot270_lane_f16(
-// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
-// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
-// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
-// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot270.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
+// CHECK: [[DUP:%.*]] = shufflevector <4 x half> %rhs, <4 x half> poison, <8 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
+// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot270.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP]])
 // CHECK: ret <8 x half> [[RES]]
 float16x8_t test_vcmlaq_rot270_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
   return vcmlaq_rot270_lane_f16(acc, lhs, rhs, 1);

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