[clang] 3b25407 - [IR] Mark zext/sext constant expressions as undesirable
Nikita Popov via cfe-commits
cfe-commits at lists.llvm.org
Mon Oct 2 03:40:30 PDT 2023
Author: Nikita Popov
Date: 2023-10-02T12:40:20+02:00
New Revision: 3b25407d977d9ed3dbcaccd4f8850b65e95d70fd
URL: https://github.com/llvm/llvm-project/commit/3b25407d977d9ed3dbcaccd4f8850b65e95d70fd
DIFF: https://github.com/llvm/llvm-project/commit/3b25407d977d9ed3dbcaccd4f8850b65e95d70fd.diff
LOG: [IR] Mark zext/sext constant expressions as undesirable
Introduce isDesirableCastOp() which determines whether IR builder
and constant folding should produce constant expressions for a
given cast type. This mirrors what we do for binary operators.
Mark zext/sext as undesirable, which prevents most creations of such
constant expressions. This is still somewhat incomplete and there
are a few more places that can create zext/sext expressions.
This is part of the work for
https://discourse.llvm.org/t/rfc-remove-most-constant-expressions/63179.
The reason for the odd result in the constantexpr-fneg.c test is
that initially the "a[]" global is created with an [0 x i32] type,
at which point the icmp expression cannot be folded. Later it is
replaced with an [1 x i32] global and the icmp gets folded away.
But at that point we no longer fold the zext.
Added:
Modified:
clang/test/CodeGen/constantexpr-fneg.c
clang/test/CodeGenCXX/weak-external.cpp
clang/test/CodeGenOpenCL/amdgpu-nullptr.cl
llvm/include/llvm/Analysis/TargetFolder.h
llvm/include/llvm/IR/ConstantFolder.h
llvm/include/llvm/IR/Constants.h
llvm/lib/Analysis/ConstantFolding.cpp
llvm/lib/IR/Constants.cpp
llvm/lib/Transforms/Utils/SCCPSolver.cpp
llvm/test/Transforms/InstCombine/constant-fold-shifts.ll
llvm/test/Transforms/InstCombine/gep-custom-dl.ll
llvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor-by-value.ll
llvm/test/Transforms/LowerTypeTests/import.ll
llvm/test/Transforms/LowerTypeTests/simplify.ll
Removed:
################################################################################
diff --git a/clang/test/CodeGen/constantexpr-fneg.c b/clang/test/CodeGen/constantexpr-fneg.c
index f82b3ff726578bb..3cd4db34f61acb7 100644
--- a/clang/test/CodeGen/constantexpr-fneg.c
+++ b/clang/test/CodeGen/constantexpr-fneg.c
@@ -8,9 +8,11 @@
// CHECK: entry:
// CHECK-NEXT: %retval = alloca i32
// CHECK-NEXT: store i32 0, ptr %retval
+// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 true to i32
+// CHECK-NEXT: [[SITOFP:%.*]] = sitofp i32 [[ZEXT]] to float
// CHECK-NEXT: [[LV:%.*]] = load ptr, ptr @c
-// CHECK-NEXT: store float 1.000000e+00, ptr [[LV]], align 4
-// CHECK-NEXT: [[FNEG:%.*]] = fneg float 1.000000e+00
+// CHECK-NEXT: store float [[SITOFP]], ptr [[LV]], align 4
+// CHECK-NEXT: [[FNEG:%.*]] = fneg float [[SITOFP]]
// CHECK-NEXT: [[CONV:%.*]] = fptosi float [[FNEG]] to i32
// CHECK-NEXT: ret i32 [[CONV]]
diff --git a/clang/test/CodeGenCXX/weak-external.cpp b/clang/test/CodeGenCXX/weak-external.cpp
index af636ccb4a3aef2..5fc37f73bb46974 100644
--- a/clang/test/CodeGenCXX/weak-external.cpp
+++ b/clang/test/CodeGenCXX/weak-external.cpp
@@ -80,19 +80,23 @@ namespace not_weak_on_first {
namespace constant_eval {
[[gnu::weak]] extern int a;
// CHECK-LABEL: define {{.*}} @__cxx_global_var_init
- // CHECK: store i8 zext (i1 icmp ne (ptr @_ZN13constant_eval1aE, ptr null) to i8), ptr @_ZN13constant_eval6has_a1E,
+ // CHECK: [[ZEXT:%.*]] = zext i1 icmp ne (ptr @_ZN13constant_eval1aE, ptr null) to i8
+ // CHECK: store i8 [[ZEXT]], ptr @_ZN13constant_eval6has_a1E,
bool has_a1 = &a;
// CHECK-LABEL: define {{.*}} @__cxx_global_var_init
- // CHECK: store i8 zext (i1 icmp ne (ptr @_ZN13constant_eval1aE, ptr null) to i8), ptr @_ZN13constant_eval6has_a2E,
+ // CHECK: [[ZEXT:%.*]] = zext i1 icmp ne (ptr @_ZN13constant_eval1aE, ptr null) to i8
+ // CHECK: store i8 [[ZEXT]], ptr @_ZN13constant_eval6has_a2E,
bool has_a2 = &a != nullptr;
struct X {
[[gnu::weak]] void f();
};
// CHECK-LABEL: define {{.*}} @__cxx_global_var_init
- // CHECK: store i8 zext (i1 icmp ne (i{{32|64}} ptrtoint (ptr @_ZN13constant_eval1X1fEv to i{{32|64}}), i{{32|64}} 0) to i8), ptr @_ZN13constant_eval6has_f1E,
+ // CHECK: [[ZEXT:%.*]] = zext i1 icmp ne (i{{32|64}} ptrtoint (ptr @_ZN13constant_eval1X1fEv to i{{32|64}}), i{{32|64}} 0) to i8
+ // CHECK: store i8 [[ZEXT]], ptr @_ZN13constant_eval6has_f1E,
bool has_f1 = &X::f;
// CHECK-LABEL: define {{.*}} @__cxx_global_var_init
- // CHECK: store i8 zext (i1 icmp ne (i{{32|64}} ptrtoint (ptr @_ZN13constant_eval1X1fEv to i{{32|64}}), i{{32|64}} 0) to i8), ptr @_ZN13constant_eval6has_f2E,
+ // CHECK: [[ZEXT:%.*]] = zext i1 icmp ne (i{{32|64}} ptrtoint (ptr @_ZN13constant_eval1X1fEv to i{{32|64}}), i{{32|64}} 0) to i8
+ // CHECK: store i8 [[ZEXT]], ptr @_ZN13constant_eval6has_f2E,
bool has_f2 = &X::f != nullptr;
}
diff --git a/clang/test/CodeGenOpenCL/amdgpu-nullptr.cl b/clang/test/CodeGenOpenCL/amdgpu-nullptr.cl
index cb3ca514c584fb1..8a04456b5df0443 100644
--- a/clang/test/CodeGenOpenCL/amdgpu-nullptr.cl
+++ b/clang/test/CodeGenOpenCL/amdgpu-nullptr.cl
@@ -606,7 +606,8 @@ int test_and_ptr(private char* p1, local char* p2) {
// NOOPT: store ptr addrspace(1) null, ptr addrspace(5) %glob, align 8
// NOOPT: %{{.*}} = sub i64 %{{.*}}, 0
// NOOPT: call void @test_fold_callee
-// NOOPT: %{{.*}} = add nsw i64 %1, sext (i32 ptrtoint (ptr addrspace(5) addrspacecast (ptr null to ptr addrspace(5)) to i32) to i64)
+// NOOPT: %[[SEXT:.*]] = sext i32 ptrtoint (ptr addrspace(5) addrspacecast (ptr null to ptr addrspace(5)) to i32) to i64
+// NOOPT: %{{.*}} = add nsw i64 %1, %[[SEXT]]
// NOOPT: %{{.*}} = sub nsw i64 %{{.*}}, 1
void test_fold_callee(void);
void test_fold_private(void) {
@@ -621,7 +622,8 @@ void test_fold_private(void) {
// NOOPT: store ptr addrspace(1) null, ptr addrspace(5) %glob, align 8
// NOOPT: %{{.*}} = sub i64 %{{.*}}, 0
// NOOPT: call void @test_fold_callee
-// NOOPT: %{{.*}} = add nsw i64 %{{.*}}, sext (i32 ptrtoint (ptr addrspace(3) addrspacecast (ptr null to ptr addrspace(3)) to i32) to i64)
+// NOOPT: %[[SEXT:.*]] = sext i32 ptrtoint (ptr addrspace(3) addrspacecast (ptr null to ptr addrspace(3)) to i32) to i64
+// NOOPT: %{{.*}} = add nsw i64 %{{.*}}, %[[SEXT]]
// NOOPT: %{{.*}} = sub nsw i64 %{{.*}}, 1
void test_fold_local(void) {
global int* glob = (test_fold_callee(), (global int*)(generic char*)0);
diff --git a/llvm/include/llvm/Analysis/TargetFolder.h b/llvm/include/llvm/Analysis/TargetFolder.h
index 4a6aec98abf861c..978e1002515fc05 100644
--- a/llvm/include/llvm/Analysis/TargetFolder.h
+++ b/llvm/include/llvm/Analysis/TargetFolder.h
@@ -187,7 +187,7 @@ class TargetFolder final : public IRBuilderFolder {
Value *FoldCast(Instruction::CastOps Op, Value *V,
Type *DestTy) const override {
if (auto *C = dyn_cast<Constant>(V))
- return Fold(ConstantExpr::getCast(Op, C, DestTy));
+ return ConstantFoldCastOperand(Op, C, DestTy, DL);
return nullptr;
}
diff --git a/llvm/include/llvm/IR/ConstantFolder.h b/llvm/include/llvm/IR/ConstantFolder.h
index 30c8b598bda6f90..c2b30a65e32e251 100644
--- a/llvm/include/llvm/IR/ConstantFolder.h
+++ b/llvm/include/llvm/IR/ConstantFolder.h
@@ -175,8 +175,11 @@ class ConstantFolder final : public IRBuilderFolder {
Value *FoldCast(Instruction::CastOps Op, Value *V,
Type *DestTy) const override {
- if (auto *C = dyn_cast<Constant>(V))
- return ConstantExpr::getCast(Op, C, DestTy);
+ if (auto *C = dyn_cast<Constant>(V)) {
+ if (ConstantExpr::isDesirableCastOp(Op))
+ return ConstantExpr::getCast(Op, C, DestTy);
+ return ConstantFoldCastInstruction(Op, C, DestTy);
+ }
return nullptr;
}
diff --git a/llvm/include/llvm/IR/Constants.h b/llvm/include/llvm/IR/Constants.h
index 710a9142d5f7202..afa1aefb44aa1aa 100644
--- a/llvm/include/llvm/IR/Constants.h
+++ b/llvm/include/llvm/IR/Constants.h
@@ -1330,6 +1330,9 @@ class ConstantExpr : public Constant {
/// supported.
static bool isSupportedBinOp(unsigned Opcode);
+ /// Whether creating a constant expression for this cast is desirable.
+ static bool isDesirableCastOp(unsigned Opcode);
+
/// Whether creating a constant expression for this getelementptr type is
/// supported.
static bool isSupportedGetElementPtr(const Type *SrcElemTy) {
diff --git a/llvm/lib/Analysis/ConstantFolding.cpp b/llvm/lib/Analysis/ConstantFolding.cpp
index fab73c20f3f2d8d..2f164e80f24060a 100644
--- a/llvm/lib/Analysis/ConstantFolding.cpp
+++ b/llvm/lib/Analysis/ConstantFolding.cpp
@@ -1435,7 +1435,7 @@ Constant *llvm::ConstantFoldCastOperand(unsigned Opcode, Constant *C,
/*IsSigned=*/false);
}
}
- return ConstantExpr::getCast(Opcode, C, DestTy);
+ break;
case Instruction::IntToPtr:
// If the input is a ptrtoint, turn the pair into a ptr to ptr bitcast if
// the int size is >= the ptr size and the address spaces are the same.
@@ -1454,8 +1454,7 @@ Constant *llvm::ConstantFoldCastOperand(unsigned Opcode, Constant *C,
}
}
}
-
- return ConstantExpr::getCast(Opcode, C, DestTy);
+ break;
case Instruction::Trunc:
case Instruction::ZExt:
case Instruction::SExt:
@@ -1466,10 +1465,14 @@ Constant *llvm::ConstantFoldCastOperand(unsigned Opcode, Constant *C,
case Instruction::FPToUI:
case Instruction::FPToSI:
case Instruction::AddrSpaceCast:
- return ConstantExpr::getCast(Opcode, C, DestTy);
+ break;
case Instruction::BitCast:
return FoldBitCast(C, DestTy, DL);
}
+
+ if (ConstantExpr::isDesirableCastOp(Opcode))
+ return ConstantExpr::getCast(Opcode, C, DestTy);
+ return ConstantFoldCastInstruction(Opcode, C, DestTy);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp
index 6589bd33be7619c..ba18da9e1ac967d 100644
--- a/llvm/lib/IR/Constants.cpp
+++ b/llvm/lib/IR/Constants.cpp
@@ -2331,6 +2331,28 @@ bool ConstantExpr::isSupportedBinOp(unsigned Opcode) {
}
}
+bool ConstantExpr::isDesirableCastOp(unsigned Opcode) {
+ switch (Opcode) {
+ case Instruction::ZExt:
+ case Instruction::SExt:
+ return false;
+ case Instruction::Trunc:
+ case Instruction::FPTrunc:
+ case Instruction::FPExt:
+ case Instruction::UIToFP:
+ case Instruction::SIToFP:
+ case Instruction::FPToUI:
+ case Instruction::FPToSI:
+ case Instruction::PtrToInt:
+ case Instruction::IntToPtr:
+ case Instruction::BitCast:
+ case Instruction::AddrSpaceCast:
+ return true;
+ default:
+ llvm_unreachable("Argument must be cast opcode");
+ }
+}
+
Constant *ConstantExpr::getSizeOf(Type* Ty) {
// sizeof is implemented as: (i64) gep (Ty*)null, 1
// Note that a non-inbounds gep is used, as null isn't within any object.
diff --git a/llvm/lib/Transforms/Utils/SCCPSolver.cpp b/llvm/lib/Transforms/Utils/SCCPSolver.cpp
index 8a67fda7c98e787..4b96b02ee2ecd66 100644
--- a/llvm/lib/Transforms/Utils/SCCPSolver.cpp
+++ b/llvm/lib/Transforms/Utils/SCCPSolver.cpp
@@ -1225,10 +1225,12 @@ void SCCPInstVisitor::visitCastInst(CastInst &I) {
if (Constant *OpC = getConstant(OpSt, I.getOperand(0)->getType())) {
// Fold the constant as we build.
- Constant *C = ConstantFoldCastOperand(I.getOpcode(), OpC, I.getType(), DL);
- markConstant(&I, C);
- } else if (I.getDestTy()->isIntegerTy() &&
- I.getSrcTy()->isIntOrIntVectorTy()) {
+ if (Constant *C =
+ ConstantFoldCastOperand(I.getOpcode(), OpC, I.getType(), DL))
+ return (void)markConstant(&I, C);
+ }
+
+ if (I.getDestTy()->isIntegerTy() && I.getSrcTy()->isIntOrIntVectorTy()) {
auto &LV = getValueState(&I);
ConstantRange OpRange = getConstantRange(OpSt, I.getSrcTy());
diff --git a/llvm/test/Transforms/InstCombine/constant-fold-shifts.ll b/llvm/test/Transforms/InstCombine/constant-fold-shifts.ll
index 5b2c8d02797544d..57d6144bbee29e6 100644
--- a/llvm/test/Transforms/InstCombine/constant-fold-shifts.ll
+++ b/llvm/test/Transforms/InstCombine/constant-fold-shifts.ll
@@ -8,7 +8,7 @@
define void @ossfuzz_14169_test1(ptr %a0) {
; CHECK-LABEL: @ossfuzz_14169_test1(
; CHECK-NEXT: bb:
-; CHECK-NEXT: store ptr undef, ptr undef, align 8
+; CHECK-NEXT: store ptr poison, ptr undef, align 8
; CHECK-NEXT: ret void
;
bb:
@@ -24,7 +24,7 @@ bb:
define void @ossfuzz_14169_test2(ptr %a0) {
; CHECK-LABEL: @ossfuzz_14169_test2(
; CHECK-NEXT: bb:
-; CHECK-NEXT: store ptr undef, ptr undef, align 8
+; CHECK-NEXT: store ptr poison, ptr undef, align 8
; CHECK-NEXT: ret void
;
bb:
diff --git a/llvm/test/Transforms/InstCombine/gep-custom-dl.ll b/llvm/test/Transforms/InstCombine/gep-custom-dl.ll
index 41285c78f03edbe..7be15e38d44a7ce 100644
--- a/llvm/test/Transforms/InstCombine/gep-custom-dl.ll
+++ b/llvm/test/Transforms/InstCombine/gep-custom-dl.ll
@@ -168,7 +168,7 @@ define i32 @test10() {
define i16 @constant_fold_custom_dl() {
; CHECK-LABEL: @constant_fold_custom_dl(
; CHECK-NEXT: entry:
-; CHECK-NEXT: ret i16 ptrtoint (ptr addrspace(1) getelementptr (i8, ptr addrspace(1) getelementptr inbounds ([1000 x i8], ptr addrspace(1) @X_as1, i32 1, i32 0), i32 sext (i16 sub (i16 0, i16 ptrtoint (ptr addrspace(1) @X_as1 to i16)) to i32)) to i16)
+; CHECK-NEXT: ret i16 ptrtoint (ptr addrspace(1) getelementptr (i8, ptr addrspace(1) getelementptr inbounds ([1000 x i8], ptr addrspace(1) @X_as1, i32 1, i32 0), i16 sub (i16 0, i16 ptrtoint (ptr addrspace(1) @X_as1 to i16))) to i16)
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor-by-value.ll b/llvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor-by-value.ll
index 3cea5aff7e704c8..db2c8e2f22f6eef 100644
--- a/llvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor-by-value.ll
+++ b/llvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor-by-value.ll
@@ -94,9 +94,11 @@ entry:
define i16 @constantexpr2() {
; CHECK-LABEL: @constantexpr2(
+; CHECK-NEXT: [[I1:%.*]] = zext i1 icmp ne (ptr getelementptr inbounds ([6 x [1 x i64]], ptr @global_constant3, i64 0, i64 5, i64 0), ptr @global_constant4) to i16
; CHECK-NEXT: [[I2:%.*]] = load ptr, ptr @global_constant5, align 1
; CHECK-NEXT: [[I3:%.*]] = load i16, ptr [[I2]], align 1
-; CHECK-NEXT: [[I5:%.*]] = xor i16 [[I3]], xor (i16 zext (i1 icmp ne (ptr getelementptr inbounds ([6 x [1 x i64]], ptr @global_constant3, i64 0, i64 5, i64 0), ptr @global_constant4) to i16), i16 -1)
+; CHECK-NEXT: [[I4:%.*]] = xor i16 [[I3]], [[I1]]
+; CHECK-NEXT: [[I5:%.*]] = xor i16 [[I4]], -1
; CHECK-NEXT: ret i16 [[I5]]
;
%i0 = icmp ne ptr getelementptr inbounds ([6 x [1 x i64]], ptr @global_constant3, i16 0, i16 5, i16 0), @global_constant4
diff --git a/llvm/test/Transforms/LowerTypeTests/import.ll b/llvm/test/Transforms/LowerTypeTests/import.ll
index abe85460ab5bb63..1eff4bbbbdf9712 100644
--- a/llvm/test/Transforms/LowerTypeTests/import.ll
+++ b/llvm/test/Transforms/LowerTypeTests/import.ll
@@ -37,11 +37,13 @@ define i1 @allones7(ptr %p) {
; X86-SAME: ptr [[P:%.*]]) {
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_allones7_global_addr to i64)
-; X86-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], zext (i8 ptrtoint (ptr @__typeid_allones7_align to i8) to i64)
-; X86-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_allones7_align to i8)) to i64)
-; X86-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
-; X86-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], ptrtoint (ptr @__typeid_allones7_size_m1 to i64)
-; X86-NEXT: ret i1 [[TMP6]]
+; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_allones7_align to i8) to i64
+; X86-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP2]], [[TMP3]]
+; X86-NEXT: [[TMP5:%.*]] = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_allones7_align to i8)) to i64
+; X86-NEXT: [[TMP6:%.*]] = shl i64 [[TMP2]], [[TMP5]]
+; X86-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]]
+; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_allones7_size_m1 to i64)
+; X86-NEXT: ret i1 [[TMP8]]
;
; ARM-LABEL: define i1 @allones7(
; ARM-SAME: ptr [[P:%.*]]) {
@@ -62,11 +64,13 @@ define i1 @allones32(ptr %p) {
; X86-SAME: ptr [[P:%.*]]) {
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_allones32_global_addr to i64)
-; X86-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], zext (i8 ptrtoint (ptr @__typeid_allones32_align to i8) to i64)
-; X86-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_allones32_align to i8)) to i64)
-; X86-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
-; X86-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], ptrtoint (ptr @__typeid_allones32_size_m1 to i64)
-; X86-NEXT: ret i1 [[TMP6]]
+; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_allones32_align to i8) to i64
+; X86-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP2]], [[TMP3]]
+; X86-NEXT: [[TMP5:%.*]] = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_allones32_align to i8)) to i64
+; X86-NEXT: [[TMP6:%.*]] = shl i64 [[TMP2]], [[TMP5]]
+; X86-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]]
+; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_allones32_size_m1 to i64)
+; X86-NEXT: ret i1 [[TMP8]]
;
; ARM-LABEL: define i1 @allones32(
; ARM-SAME: ptr [[P:%.*]]) {
@@ -87,20 +91,22 @@ define i1 @bytearray7(ptr %p) {
; X86-SAME: ptr [[P:%.*]]) {
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray7_global_addr to i64)
-; X86-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], zext (i8 ptrtoint (ptr @__typeid_bytearray7_align to i8) to i64)
-; X86-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_bytearray7_align to i8)) to i64)
-; X86-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
-; X86-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
-; X86-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]]
-; X86: 7:
-; X86-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP5]]
-; X86-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
-; X86-NEXT: [[TMP10:%.*]] = and i8 [[TMP9]], ptrtoint (ptr @__typeid_bytearray7_bit_mask to i8)
-; X86-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP10]], 0
-; X86-NEXT: br label [[TMP12]]
-; X86: 12:
-; X86-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP11]], [[TMP7]] ]
-; X86-NEXT: ret i1 [[TMP13]]
+; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_bytearray7_align to i8) to i64
+; X86-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP2]], [[TMP3]]
+; X86-NEXT: [[TMP5:%.*]] = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_bytearray7_align to i8)) to i64
+; X86-NEXT: [[TMP6:%.*]] = shl i64 [[TMP2]], [[TMP5]]
+; X86-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]]
+; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
+; X86-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP14:%.*]]
+; X86: 9:
+; X86-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP7]]
+; X86-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1
+; X86-NEXT: [[TMP12:%.*]] = and i8 [[TMP11]], ptrtoint (ptr @__typeid_bytearray7_bit_mask to i8)
+; X86-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
+; X86-NEXT: br label [[TMP14]]
+; X86: 14:
+; X86-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], [[TMP9]] ]
+; X86-NEXT: ret i1 [[TMP15]]
;
; ARM-LABEL: define i1 @bytearray7(
; ARM-SAME: ptr [[P:%.*]]) {
@@ -130,20 +136,22 @@ define i1 @bytearray32(ptr %p) {
; X86-SAME: ptr [[P:%.*]]) {
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray32_global_addr to i64)
-; X86-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], zext (i8 ptrtoint (ptr @__typeid_bytearray32_align to i8) to i64)
-; X86-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_bytearray32_align to i8)) to i64)
-; X86-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
-; X86-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], ptrtoint (ptr @__typeid_bytearray32_size_m1 to i64)
-; X86-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]]
-; X86: 7:
-; X86-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP5]]
-; X86-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
-; X86-NEXT: [[TMP10:%.*]] = and i8 [[TMP9]], ptrtoint (ptr @__typeid_bytearray32_bit_mask to i8)
-; X86-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP10]], 0
-; X86-NEXT: br label [[TMP12]]
-; X86: 12:
-; X86-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP11]], [[TMP7]] ]
-; X86-NEXT: ret i1 [[TMP13]]
+; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_bytearray32_align to i8) to i64
+; X86-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP2]], [[TMP3]]
+; X86-NEXT: [[TMP5:%.*]] = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_bytearray32_align to i8)) to i64
+; X86-NEXT: [[TMP6:%.*]] = shl i64 [[TMP2]], [[TMP5]]
+; X86-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]]
+; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_bytearray32_size_m1 to i64)
+; X86-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP14:%.*]]
+; X86: 9:
+; X86-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP7]]
+; X86-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1
+; X86-NEXT: [[TMP12:%.*]] = and i8 [[TMP11]], ptrtoint (ptr @__typeid_bytearray32_bit_mask to i8)
+; X86-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
+; X86-NEXT: br label [[TMP14]]
+; X86: 14:
+; X86-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], [[TMP9]] ]
+; X86-NEXT: ret i1 [[TMP15]]
;
; ARM-LABEL: define i1 @bytearray32(
; ARM-SAME: ptr [[P:%.*]]) {
@@ -173,21 +181,23 @@ define i1 @inline5(ptr %p) {
; X86-SAME: ptr [[P:%.*]]) {
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_inline5_global_addr to i64)
-; X86-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], zext (i8 ptrtoint (ptr @__typeid_inline5_align to i8) to i64)
-; X86-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_inline5_align to i8)) to i64)
-; X86-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
-; X86-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], ptrtoint (ptr @__typeid_inline5_size_m1 to i64)
-; X86-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP13:%.*]]
-; X86: 7:
-; X86-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP5]] to i32
-; X86-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 31
-; X86-NEXT: [[TMP10:%.*]] = shl i32 1, [[TMP9]]
-; X86-NEXT: [[TMP11:%.*]] = and i32 ptrtoint (ptr @__typeid_inline5_inline_bits to i32), [[TMP10]]
-; X86-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
-; X86-NEXT: br label [[TMP13]]
-; X86: 13:
-; X86-NEXT: [[TMP14:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP12]], [[TMP7]] ]
-; X86-NEXT: ret i1 [[TMP14]]
+; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_inline5_align to i8) to i64
+; X86-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP2]], [[TMP3]]
+; X86-NEXT: [[TMP5:%.*]] = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_inline5_align to i8)) to i64
+; X86-NEXT: [[TMP6:%.*]] = shl i64 [[TMP2]], [[TMP5]]
+; X86-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]]
+; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_inline5_size_m1 to i64)
+; X86-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP15:%.*]]
+; X86: 9:
+; X86-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP7]] to i32
+; X86-NEXT: [[TMP11:%.*]] = and i32 [[TMP10]], 31
+; X86-NEXT: [[TMP12:%.*]] = shl i32 1, [[TMP11]]
+; X86-NEXT: [[TMP13:%.*]] = and i32 ptrtoint (ptr @__typeid_inline5_inline_bits to i32), [[TMP12]]
+; X86-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
+; X86-NEXT: br label [[TMP15]]
+; X86: 15:
+; X86-NEXT: [[TMP16:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP14]], [[TMP9]] ]
+; X86-NEXT: ret i1 [[TMP16]]
;
; ARM-LABEL: define i1 @inline5(
; ARM-SAME: ptr [[P:%.*]]) {
@@ -218,20 +228,22 @@ define i1 @inline6(ptr %p) {
; X86-SAME: ptr [[P:%.*]]) {
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_inline6_global_addr to i64)
-; X86-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], zext (i8 ptrtoint (ptr @__typeid_inline6_align to i8) to i64)
-; X86-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_inline6_align to i8)) to i64)
-; X86-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
-; X86-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], ptrtoint (ptr @__typeid_inline6_size_m1 to i64)
-; X86-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]]
-; X86: 7:
-; X86-NEXT: [[TMP8:%.*]] = and i64 [[TMP5]], 63
-; X86-NEXT: [[TMP9:%.*]] = shl i64 1, [[TMP8]]
-; X86-NEXT: [[TMP10:%.*]] = and i64 ptrtoint (ptr @__typeid_inline6_inline_bits to i64), [[TMP9]]
-; X86-NEXT: [[TMP11:%.*]] = icmp ne i64 [[TMP10]], 0
-; X86-NEXT: br label [[TMP12]]
-; X86: 12:
-; X86-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP11]], [[TMP7]] ]
-; X86-NEXT: ret i1 [[TMP13]]
+; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_inline6_align to i8) to i64
+; X86-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP2]], [[TMP3]]
+; X86-NEXT: [[TMP5:%.*]] = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_inline6_align to i8)) to i64
+; X86-NEXT: [[TMP6:%.*]] = shl i64 [[TMP2]], [[TMP5]]
+; X86-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]]
+; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_inline6_size_m1 to i64)
+; X86-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP14:%.*]]
+; X86: 9:
+; X86-NEXT: [[TMP10:%.*]] = and i64 [[TMP7]], 63
+; X86-NEXT: [[TMP11:%.*]] = shl i64 1, [[TMP10]]
+; X86-NEXT: [[TMP12:%.*]] = and i64 ptrtoint (ptr @__typeid_inline6_inline_bits to i64), [[TMP11]]
+; X86-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP12]], 0
+; X86-NEXT: br label [[TMP14]]
+; X86: 14:
+; X86-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], [[TMP9]] ]
+; X86-NEXT: ret i1 [[TMP15]]
;
; ARM-LABEL: define i1 @inline6(
; ARM-SAME: ptr [[P:%.*]]) {
diff --git a/llvm/test/Transforms/LowerTypeTests/simplify.ll b/llvm/test/Transforms/LowerTypeTests/simplify.ll
index 3ad856d9bb24b8b..ff0f941eece9931 100644
--- a/llvm/test/Transforms/LowerTypeTests/simplify.ll
+++ b/llvm/test/Transforms/LowerTypeTests/simplify.ll
@@ -11,17 +11,19 @@ define i1 @bytearray7(ptr %p) {
; CHECK-SAME: ptr [[P:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray7_global_addr to i64)
-; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], zext (i8 ptrtoint (ptr @__typeid_bytearray7_align to i8) to i64)
-; CHECK-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_bytearray7_align to i8)) to i64)
-; CHECK-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
-; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[F:%.*]]
-; CHECK: 7:
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP5]]
-; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
-; CHECK-NEXT: [[TMP10:%.*]] = and i8 [[TMP9]], ptrtoint (ptr @__typeid_bytearray7_bit_mask to i8)
-; CHECK-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP10]], 0
-; CHECK-NEXT: br i1 [[TMP11]], label [[T:%.*]], label [[F]]
+; CHECK-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_bytearray7_align to i8) to i64
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_bytearray7_align to i8)) to i64
+; CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP2]], [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
+; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[F:%.*]]
+; CHECK: 9:
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP7]]
+; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1
+; CHECK-NEXT: [[TMP12:%.*]] = and i8 [[TMP11]], ptrtoint (ptr @__typeid_bytearray7_bit_mask to i8)
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label [[T:%.*]], label [[F]]
; CHECK: t:
; CHECK-NEXT: ret i1 true
; CHECK: f:
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