[PATCH] D145214: [TSAN] add support for riscv64

[Fangrui Song via Phabricator via cfe-commits]

MaskRay added inline comments.


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Comment at: compiler-rt/lib/tsan/rtl/tsan_platform.h:971
     };
-    const uptr indicator = 0x0e0000000000ull;
+    const uptr indicator = 0x0f0000000000ull;
     const uptr ind_lsb = 1ull << LeastSignificantSetBitIndex(indicator);
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alexfanqi wrote:
> jrtc27 wrote:
> > ?
> This is changed for sv48. Tsan compresses the address to 44 bits and uses the top 3 bits (42-44) to uncompress it by comparing with the corresponding bits in the mapping. So the 42-44th bits of each app mapping range must be all different from each other.  But 3 bits are not enough to distinguish mappings in this scheme of MappingRiscv64_48, so I increment it to 4 bits. An alternative of this would be reducing app mapping size by half.
@dvyukov ^


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145214/new/

https://reviews.llvm.org/D145214