[clang] [clang] Enable descriptions for --print-supported-extensions (PR #66715)

Balint Cristian via cfe-commits cfe-commits at lists.llvm.org
Tue Sep 19 20:13:14 PDT 2023


https://github.com/cbalint13 updated https://github.com/llvm/llvm-project/pull/66715

>From 4ef7b54508b7ff3f17f29d1763b90b963a8f390e Mon Sep 17 00:00:00 2001
From: Balint Cristian <cristian.balint at gmail.com>
Date: Wed, 20 Sep 2023 06:12:52 +0300
Subject: [PATCH] [clang] Enable descriptions for --print-supported-extensions

---
 .../test/Driver/print-supported-extensions.c  |   3 +
 clang/tools/driver/cc1_main.cpp               |  14 +-
 llvm/include/llvm/MC/MCSubtargetInfo.h        |   7 +
 llvm/include/llvm/Support/RISCVISAInfo.h      |   4 +-
 .../llvm/TargetParser/AArch64TargetParser.h   |   3 +-
 .../llvm/TargetParser/ARMTargetParser.h       |   3 +-
 llvm/lib/Support/RISCVISAInfo.cpp             |  36 ++-
 llvm/lib/TargetParser/AArch64TargetParser.cpp |  18 +-
 llvm/lib/TargetParser/ARMTargetParser.cpp     |  17 +-
 llvm/unittests/Support/RISCVISAInfoTest.cpp   | 244 +++++++++---------
 .../TargetParser/TargetParserTest.cpp         |  23 +-
 11 files changed, 224 insertions(+), 148 deletions(-)

diff --git a/clang/test/Driver/print-supported-extensions.c b/clang/test/Driver/print-supported-extensions.c
index 8daf4d8a34b8a60..af731a5db202055 100644
--- a/clang/test/Driver/print-supported-extensions.c
+++ b/clang/test/Driver/print-supported-extensions.c
@@ -4,14 +4,17 @@
 // RUN: %if aarch64-registered-target %{ %clang --target=aarch64-linux-gnu \
 // RUN:   --print-supported-extensions 2>&1 | FileCheck %s --check-prefix AARCH64 %}
 // AARCH64: All available -march extensions for AArch64
+// AARCH64:     Name                Description
 
 // RUN: %if riscv-registered-target %{ %clang --target=riscv64-linux-gnu \
 // RUN:   --print-supported-extensions 2>&1 | FileCheck %s --check-prefix RISCV %}
 // RISCV: All available -march extensions for RISC-V
+// RISCV:     Name                Version   Description
 
 // RUN: %if arm-registered-target %{ %clang --target=arm-linux-gnu \
 // RUN:   --print-supported-extensions 2>&1 | FileCheck %s --check-prefix ARM %}
 // ARM: All available -march extensions for ARM
+// ARM:     Name                Description
 
 // RUN: %if x86-registered-target %{ not %clang --target=x86_64-linux-gnu \
 // RUN:   --print-supported-extensions 2>&1 | FileCheck %s --check-prefix X86 %}
diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index f0d7b5c3889dc1f..3b49dc414c2bd6a 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -28,6 +28,7 @@
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Config/llvm-config.h"
 #include "llvm/LinkAllPasses.h"
+#include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Option/Arg.h"
 #include "llvm/Option/ArgList.h"
@@ -198,13 +199,20 @@ static int PrintSupportedExtensions(std::string TargetStr) {
   std::unique_ptr<llvm::TargetMachine> TheTargetMachine(
       TheTarget->createTargetMachine(TargetStr, "", "", Options, std::nullopt));
   const llvm::Triple &MachineTriple = TheTargetMachine->getTargetTriple();
+  const llvm::MCSubtargetInfo *MCInfo = TheTargetMachine->getMCSubtargetInfo();
+  const llvm::ArrayRef<llvm::SubtargetFeatureKV> Features =
+    MCInfo->getAllProcessorFeatures();
+
+  llvm::StringMap<llvm::StringRef> llvmDescMap;
+  for (const llvm::SubtargetFeatureKV &feature : Features)
+    llvmDescMap.insert({feature.Key, feature.Desc});
 
   if (MachineTriple.isRISCV())
-    llvm::riscvExtensionsHelp();
+    llvm::riscvExtensionsHelp(llvmDescMap);
   else if (MachineTriple.isAArch64())
-    llvm::AArch64::PrintSupportedExtensions();
+    llvm::AArch64::PrintSupportedExtensions(llvmDescMap);
   else if (MachineTriple.isARM())
-    llvm::ARM::PrintSupportedExtensions();
+    llvm::ARM::PrintSupportedExtensions(llvmDescMap);
   else {
     // The option was already checked in Driver::HandleImmediateArgs,
     // so we do not expect to get here if we are not a supported architecture.
diff --git a/llvm/include/llvm/MC/MCSubtargetInfo.h b/llvm/include/llvm/MC/MCSubtargetInfo.h
index c1533ac8d0059f5..45c58988985e638 100644
--- a/llvm/include/llvm/MC/MCSubtargetInfo.h
+++ b/llvm/include/llvm/MC/MCSubtargetInfo.h
@@ -230,10 +230,17 @@ class MCSubtargetInfo {
     return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
   }
 
+  /// Return processor descriptions.
   ArrayRef<SubtargetSubTypeKV> getAllProcessorDescriptions() const {
     return ProcDesc;
   }
 
+  /// Return processor features.
+  ArrayRef<SubtargetFeatureKV> getAllProcessorFeatures() const {
+    return ProcFeatures;
+  }
+
+
   virtual unsigned getHwMode() const { return 0; }
 
   /// Return the cache size in bytes for the given level of cache.
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h b/llvm/include/llvm/Support/RISCVISAInfo.h
index 9092fe5c272a994..87fbc7f6fcaf9f6 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/Support/RISCVISAInfo.h
@@ -9,6 +9,7 @@
 #ifndef LLVM_SUPPORT_RISCVISAINFO_H
 #define LLVM_SUPPORT_RISCVISAINFO_H
 
+#include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/Error.h"
 
@@ -22,7 +23,8 @@ struct RISCVExtensionInfo {
   unsigned MinorVersion;
 };
 
-void riscvExtensionsHelp();
+void getAllExtensions(StringMap<RISCVExtensionInfo> &Features);
+void riscvExtensionsHelp(llvm::StringMap<llvm::StringRef> llvmDescMap);
 
 class RISCVISAInfo {
 public:
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 190f482044083c0..6e4fda995d4c336 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -16,6 +16,7 @@
 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/Bitset.h"
+#include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/VersionTuple.h"
 #include <array>
@@ -663,7 +664,7 @@ bool isX18ReservedByDefault(const Triple &TT);
 // themselves, they are sequential (0, 1, 2, 3, ...).
 uint64_t getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs);
 
-void PrintSupportedExtensions();
+void PrintSupportedExtensions(StringMap<StringRef> llvmDescMap);
 
 } // namespace AArch64
 } // namespace llvm
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.h b/llvm/include/llvm/TargetParser/ARMTargetParser.h
index 37a358d1fa415c9..d1c9e9250c025b5 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.h
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.h
@@ -14,6 +14,7 @@
 #ifndef LLVM_TARGETPARSER_ARMTARGETPARSER_H
 #define LLVM_TARGETPARSER_ARMTARGETPARSER_H
 
+#include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/ARMBuildAttributes.h"
 #include "llvm/TargetParser/ARMTargetParserCommon.h"
@@ -259,7 +260,7 @@ StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU);
 /// string then the triple's arch name is used.
 StringRef getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch = {});
 
-void PrintSupportedExtensions();
+void PrintSupportedExtensions(StringMap<StringRef> llvmDescMap);
 
 } // namespace ARM
 } // namespace llvm
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index a3045657e63b724..a391be364e39f71 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -210,24 +210,42 @@ static void verifyTables() {
 #endif
 }
 
-void llvm::riscvExtensionsHelp() {
-  outs() << "All available -march extensions for RISC-V\n\n";
-  outs() << '\t' << left_justify("Name", 20) << "Version\n";
+void llvm::getAllExtensions(StringMap<RISCVExtensionInfo> &ExtMap) {
+  for (const auto &E : SupportedExtensions)
+    ExtMap[E.Name] = {E.Version.Major, E.Version.Minor};
+  for (const auto &E : SupportedExperimentalExtensions)
+    ExtMap[(StringRef("experimental-") + E.Name).str().c_str()] = {
+        E.Version.Major, E.Version.Minor};
+}
+
+void llvm::riscvExtensionsHelp(llvm::StringMap<llvm::StringRef> llvmDescMap) {
+
+  outs() << "All available -march extensions for RISC-V\n\n"
+         << "    " << left_justify("Name", 20) << left_justify("Version", 10)
+         << (llvmDescMap.empty() ? "\n" : "Description\n");
 
   RISCVISAInfo::OrderedExtensionMap ExtMap;
   for (const auto &E : SupportedExtensions)
     ExtMap[E.Name] = {E.Version.Major, E.Version.Minor};
-  for (const auto &E : ExtMap)
-    outs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
-                     E.second.MinorVersion);
+  for (const auto &E : ExtMap) {
+    StringRef Version(std::to_string(E.second.MajorVersion) + "." +
+                      std::to_string(E.second.MinorVersion));
+    outs() << format("    %-20s%-10s", E.first.c_str(), Version.str().c_str())
+           << format(llvmDescMap.empty() ? "\n" : "%s\n",
+                     llvmDescMap[E.first].str().c_str());
+  }
 
   outs() << "\nExperimental extensions\n";
   ExtMap.clear();
   for (const auto &E : SupportedExperimentalExtensions)
     ExtMap[E.Name] = {E.Version.Major, E.Version.Minor};
-  for (const auto &E : ExtMap)
-    outs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
-                     E.second.MinorVersion);
+  for (const auto &E : ExtMap) {
+    StringRef Version(std::to_string(E.second.MajorVersion) + "." +
+                      std::to_string(E.second.MinorVersion));
+    outs() << format("    %-20s%-10s", E.first.c_str(), Version.str().c_str())
+           << format(llvmDescMap.empty() ? "\n" : "%s\n",
+                     llvmDescMap["experimental-" + E.first].str().c_str());
+  }
 
   outs() << "\nUse -march to specify the target's extension.\n"
             "For example, clang -march=rv32i_v1p0\n";
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index 166cf880ad4a895..7b41e733aa1dfe3 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -11,8 +11,9 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/TargetParser/AArch64TargetParser.h"
+#include "llvm/Support/Format.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/TargetParser/AArch64TargetParser.h"
 #include "llvm/TargetParser/ARMTargetParserCommon.h"
 #include "llvm/TargetParser/Triple.h"
 #include <cctype>
@@ -135,11 +136,18 @@ std::optional<AArch64::CpuInfo> AArch64::parseCpu(StringRef Name) {
   return {};
 }
 
-void AArch64::PrintSupportedExtensions() {
-  outs() << "All available -march extensions for AArch64\n\n";
+void AArch64::PrintSupportedExtensions(StringMap<StringRef> llvmDescMap) {
+
+  outs() << "All available -march extensions for AArch64\n\n"
+         << "    " << left_justify("Name", 20)
+         << (llvmDescMap.empty() ? "\n" : "Description\n");
+
   for (const auto &Ext : Extensions) {
     // Extensions without a feature cannot be used with -march.
-    if (!Ext.Feature.empty())
-      outs() << '\t' << Ext.Name << "\n";
+    if (!Ext.Feature.empty()) {
+      outs() << format("    %-20s", Ext.Name.str().c_str())
+             << format(llvmDescMap.empty() ? "\n" : "%s\n",
+                       llvmDescMap[Ext.Name].str().c_str());
+    }
   }
 }
diff --git a/llvm/lib/TargetParser/ARMTargetParser.cpp b/llvm/lib/TargetParser/ARMTargetParser.cpp
index 7bf7914e9c53163..baea4b96ffbc988 100644
--- a/llvm/lib/TargetParser/ARMTargetParser.cpp
+++ b/llvm/lib/TargetParser/ARMTargetParser.cpp
@@ -11,9 +11,10 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/TargetParser/ARMTargetParser.h"
 #include "llvm/ADT/StringSwitch.h"
+#include "llvm/Support/Format.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/TargetParser/ARMTargetParser.h"
 #include "llvm/TargetParser/ARMTargetParserCommon.h"
 #include "llvm/TargetParser/Triple.h"
 #include <cctype>
@@ -600,11 +601,17 @@ StringRef ARM::getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch) {
   llvm_unreachable("invalid arch name");
 }
 
-void ARM::PrintSupportedExtensions() {
-  outs() << "All available -march extensions for ARM\n\n";
+void ARM::PrintSupportedExtensions(llvm::StringMap<llvm::StringRef> llvmDescMap) {
+  outs() << "All available -march extensions for ARM\n\n"
+         << "    " << left_justify("Name", 20)
+         << (llvmDescMap.empty() ? "\n" : "Description\n");
+
   for (const auto &Ext : ARCHExtNames) {
     // Extensions without a feature cannot be used with -march.
-    if (!Ext.Feature.empty())
-      outs() << '\t' << Ext.Name << "\n";
+    if (!Ext.Feature.empty()) {
+      outs() << format("    %-20s", Ext.Name.str().c_str())
+             << format(llvmDescMap.empty() ? "\n" : "%s\n",
+                       llvmDescMap[Ext.Name].str().c_str());
+    }
   }
 }
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index a285baa57a2a6f5..52c71ddb6eca1ab 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -6,6 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/ADT/StringMap.h"
 #include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Testing/Support/Error.h"
 #include "gtest/gtest.h"
@@ -631,134 +632,139 @@ TEST(RiscvExtensionsHelp, CheckExtensions) {
   std::string ExpectedOutput =
 R"(All available -march extensions for RISC-V
 
-	Name                Version
-	i                   2.1
-	e                   2.0
-	m                   2.0
-	a                   2.1
-	f                   2.2
-	d                   2.2
-	c                   2.0
-	v                   1.0
-	h                   1.0
-	zicbom              1.0
-	zicbop              1.0
-	zicboz              1.0
-	zicntr              2.0
-	zicsr               2.0
-	zifencei            2.0
-	zihintntl           1.0
-	zihintpause         2.0
-	zihpm               2.0
-	zmmul               1.0
-	zawrs               1.0
-	zfh                 1.0
-	zfhmin              1.0
-	zfinx               1.0
-	zdinx               1.0
-	zca                 1.0
-	zcb                 1.0
-	zcd                 1.0
-	zce                 1.0
-	zcf                 1.0
-	zcmp                1.0
-	zcmt                1.0
-	zba                 1.0
-	zbb                 1.0
-	zbc                 1.0
-	zbkb                1.0
-	zbkc                1.0
-	zbkx                1.0
-	zbs                 1.0
-	zk                  1.0
-	zkn                 1.0
-	zknd                1.0
-	zkne                1.0
-	zknh                1.0
-	zkr                 1.0
-	zks                 1.0
-	zksed               1.0
-	zksh                1.0
-	zkt                 1.0
-	zve32f              1.0
-	zve32x              1.0
-	zve64d              1.0
-	zve64f              1.0
-	zve64x              1.0
-	zvfh                1.0
-	zvfhmin             1.0
-	zvl1024b            1.0
-	zvl128b             1.0
-	zvl16384b           1.0
-	zvl2048b            1.0
-	zvl256b             1.0
-	zvl32768b           1.0
-	zvl32b              1.0
-	zvl4096b            1.0
-	zvl512b             1.0
-	zvl64b              1.0
-	zvl65536b           1.0
-	zvl8192b            1.0
-	zhinx               1.0
-	zhinxmin            1.0
-	svinval             1.0
-	svnapot             1.0
-	svpbmt              1.0
-	xcvalu              1.0
-	xcvbi               1.0
-	xcvbitmanip         1.0
-	xcvmac              1.0
-	xcvsimd             1.0
-	xsfcie              1.0
-	xsfvcp              1.0
-	xtheadba            1.0
-	xtheadbb            1.0
-	xtheadbs            1.0
-	xtheadcmo           1.0
-	xtheadcondmov       1.0
-	xtheadfmemidx       1.0
-	xtheadmac           1.0
-	xtheadmemidx        1.0
-	xtheadmempair       1.0
-	xtheadsync          1.0
-	xtheadvdot          1.0
-	xventanacondops     1.0
+    Name                Version   Description
+    i                   2.1       This is a long dummy description
+    e                   2.0       This is a long dummy description
+    m                   2.0       This is a long dummy description
+    a                   2.1       This is a long dummy description
+    f                   2.2       This is a long dummy description
+    d                   2.2       This is a long dummy description
+    c                   2.0       This is a long dummy description
+    v                   1.0       This is a long dummy description
+    h                   1.0       This is a long dummy description
+    zicbom              1.0       This is a long dummy description
+    zicbop              1.0       This is a long dummy description
+    zicboz              1.0       This is a long dummy description
+    zicntr              2.0       This is a long dummy description
+    zicsr               2.0       This is a long dummy description
+    zifencei            2.0       This is a long dummy description
+    zihintntl           1.0       This is a long dummy description
+    zihintpause         2.0       This is a long dummy description
+    zihpm               2.0       This is a long dummy description
+    zmmul               1.0       This is a long dummy description
+    zawrs               1.0       This is a long dummy description
+    zfh                 1.0       This is a long dummy description
+    zfhmin              1.0       This is a long dummy description
+    zfinx               1.0       This is a long dummy description
+    zdinx               1.0       This is a long dummy description
+    zca                 1.0       This is a long dummy description
+    zcb                 1.0       This is a long dummy description
+    zcd                 1.0       This is a long dummy description
+    zce                 1.0       This is a long dummy description
+    zcf                 1.0       This is a long dummy description
+    zcmp                1.0       This is a long dummy description
+    zcmt                1.0       This is a long dummy description
+    zba                 1.0       This is a long dummy description
+    zbb                 1.0       This is a long dummy description
+    zbc                 1.0       This is a long dummy description
+    zbkb                1.0       This is a long dummy description
+    zbkc                1.0       This is a long dummy description
+    zbkx                1.0       This is a long dummy description
+    zbs                 1.0       This is a long dummy description
+    zk                  1.0       This is a long dummy description
+    zkn                 1.0       This is a long dummy description
+    zknd                1.0       This is a long dummy description
+    zkne                1.0       This is a long dummy description
+    zknh                1.0       This is a long dummy description
+    zkr                 1.0       This is a long dummy description
+    zks                 1.0       This is a long dummy description
+    zksed               1.0       This is a long dummy description
+    zksh                1.0       This is a long dummy description
+    zkt                 1.0       This is a long dummy description
+    zve32f              1.0       This is a long dummy description
+    zve32x              1.0       This is a long dummy description
+    zve64d              1.0       This is a long dummy description
+    zve64f              1.0       This is a long dummy description
+    zve64x              1.0       This is a long dummy description
+    zvfh                1.0       This is a long dummy description
+    zvfhmin             1.0       This is a long dummy description
+    zvl1024b            1.0       This is a long dummy description
+    zvl128b             1.0       This is a long dummy description
+    zvl16384b           1.0       This is a long dummy description
+    zvl2048b            1.0       This is a long dummy description
+    zvl256b             1.0       This is a long dummy description
+    zvl32768b           1.0       This is a long dummy description
+    zvl32b              1.0       This is a long dummy description
+    zvl4096b            1.0       This is a long dummy description
+    zvl512b             1.0       This is a long dummy description
+    zvl64b              1.0       This is a long dummy description
+    zvl65536b           1.0       This is a long dummy description
+    zvl8192b            1.0       This is a long dummy description
+    zhinx               1.0       This is a long dummy description
+    zhinxmin            1.0       This is a long dummy description
+    svinval             1.0       This is a long dummy description
+    svnapot             1.0       This is a long dummy description
+    svpbmt              1.0       This is a long dummy description
+    xcvalu              1.0       This is a long dummy description
+    xcvbi               1.0       This is a long dummy description
+    xcvbitmanip         1.0       This is a long dummy description
+    xcvmac              1.0       This is a long dummy description
+    xcvsimd             1.0       This is a long dummy description
+    xsfcie              1.0       This is a long dummy description
+    xsfvcp              1.0       This is a long dummy description
+    xtheadba            1.0       This is a long dummy description
+    xtheadbb            1.0       This is a long dummy description
+    xtheadbs            1.0       This is a long dummy description
+    xtheadcmo           1.0       This is a long dummy description
+    xtheadcondmov       1.0       This is a long dummy description
+    xtheadfmemidx       1.0       This is a long dummy description
+    xtheadmac           1.0       This is a long dummy description
+    xtheadmemidx        1.0       This is a long dummy description
+    xtheadmempair       1.0       This is a long dummy description
+    xtheadsync          1.0       This is a long dummy description
+    xtheadvdot          1.0       This is a long dummy description
+    xventanacondops     1.0       This is a long dummy description
 
 Experimental extensions
-	zicfilp             0.2
-	zicond              1.0
-	zacas               1.0
-	zfa                 0.2
-	zfbfmin             0.8
-	ztso                0.1
-	zvbb                1.0
-	zvbc                1.0
-	zvfbfmin            0.8
-	zvfbfwma            0.8
-	zvkb                1.0
-	zvkg                1.0
-	zvkn                1.0
-	zvknc               1.0
-	zvkned              1.0
-	zvkng               1.0
-	zvknha              1.0
-	zvknhb              1.0
-	zvks                1.0
-	zvksc               1.0
-	zvksed              1.0
-	zvksg               1.0
-	zvksh               1.0
-	zvkt                1.0
-	smaia               1.0
-	ssaia               1.0
+    zicfilp             0.2       This is a long dummy description
+    zicond              1.0       This is a long dummy description
+    zacas               1.0       This is a long dummy description
+    zfa                 0.2       This is a long dummy description
+    zfbfmin             0.8       This is a long dummy description
+    ztso                0.1       This is a long dummy description
+    zvbb                1.0       This is a long dummy description
+    zvbc                1.0       This is a long dummy description
+    zvfbfmin            0.8       This is a long dummy description
+    zvfbfwma            0.8       This is a long dummy description
+    zvkb                1.0       This is a long dummy description
+    zvkg                1.0       This is a long dummy description
+    zvkn                1.0       This is a long dummy description
+    zvknc               1.0       This is a long dummy description
+    zvkned              1.0       This is a long dummy description
+    zvkng               1.0       This is a long dummy description
+    zvknha              1.0       This is a long dummy description
+    zvknhb              1.0       This is a long dummy description
+    zvks                1.0       This is a long dummy description
+    zvksc               1.0       This is a long dummy description
+    zvksed              1.0       This is a long dummy description
+    zvksg               1.0       This is a long dummy description
+    zvksh               1.0       This is a long dummy description
+    zvkt                1.0       This is a long dummy description
+    smaia               1.0       This is a long dummy description
+    ssaia               1.0       This is a long dummy description
 
 Use -march to specify the target's extension.
 For example, clang -march=rv32i_v1p0)";
 
   outs().flush();
   testing::internal::CaptureStdout();
+  llvm::StringMap<llvm::StringRef> DummyMap;
+  llvm::StringMap<llvm::RISCVExtensionInfo> ExtMap;
+  llvm::getAllExtensions(ExtMap);
+  for (const auto &E : ExtMap)
+    DummyMap.insert({E.first(), "This is a long dummy description"});
 
-  llvm::riscvExtensionsHelp();
+  llvm::riscvExtensionsHelp(DummyMap);
   outs().flush();
 
   std::string CapturedOutput = testing::internal::GetCapturedStdout();
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 8223f9f575135dc..f5545cf08f99c07 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -8,6 +8,7 @@
 
 #include "llvm/TargetParser/TargetParser.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/Support/ARMBuildAttributes.h"
 #include "llvm/Support/FormatVariadic.h"
@@ -1012,11 +1013,18 @@ TEST(TargetParserTest, getARMCPUForArch) {
 
 TEST(TargetParserTest, ARMPrintSupportedExtensions) {
   std::string expected = "All available -march extensions for ARM\n\n"
-                         "\tcrc\n\tcrypto\n\tsha2";
+                         "    Name                Description\n"
+                         "    crc                 This is a long dummy description\n"
+                         "    crypto              This is a long dummy description\n"
+                         "    sha2                This is a long dummy description\n";
 
   outs().flush();
   testing::internal::CaptureStdout();
-  ARM::PrintSupportedExtensions();
+  llvm::StringMap<llvm::StringRef> DummyMap;
+  for (const auto &E : llvm::ARM::ARCHExtNames)
+    DummyMap.insert({E.Name, "This is a long dummy description"});
+
+  ARM::PrintSupportedExtensions(DummyMap);
   outs().flush();
   std::string captured = testing::internal::GetCapturedStdout();
 
@@ -1932,11 +1940,18 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
 
 TEST(TargetParserTest, AArch64PrintSupportedExtensions) {
   std::string expected = "All available -march extensions for AArch64\n\n"
-                         "\taes\n\tb16b16\n\tbf16";
+                         "    Name                Description\n"
+                         "    aes                 This is a long dummy description\n"
+                         "    b16b16              This is a long dummy description\n"
+                         "    bf16                This is a long dummy description\n";
 
   outs().flush();
   testing::internal::CaptureStdout();
-  AArch64::PrintSupportedExtensions();
+  llvm::StringMap<llvm::StringRef> DummyMap;
+  for (const auto &E : llvm::AArch64::Extensions)
+    DummyMap.insert({E.Name, "This is a long dummy description"});
+
+  AArch64::PrintSupportedExtensions(DummyMap);
   outs().flush();
   std::string captured = testing::internal::GetCapturedStdout();
 



More information about the cfe-commits mailing list