[clang] [NFC][CodeGen] Change CodeGenOpt::{Level, FileType} into enum classes (PR #66295)
Arthur Eubanks via cfe-commits
cfe-commits at lists.llvm.org
Wed Sep 13 14:39:43 PDT 2023
https://github.com/aeubanks created https://github.com/llvm/llvm-project/pull/66295:
This will make it easy for callers to see issues with and fix up calls
to createTargetMachine after a future change to the params of
TargetMachine.
This matches other enums in the CodeGenOpt namespace.
For downstream users, this should be a fairly straightforward replacement,
e.g. s/CodeGenOpt::Aggressive/CodeGenOpt::Level::Aggressive
or s/CodeGenOpt::CGFT_Null/CodeGenOpt::FileType::Null
>From 855e4ce1784884f3705549490da1bdb68d2af13c Mon Sep 17 00:00:00 2001
From: Arthur Eubanks <aeubanks at google.com>
Date: Wed, 13 Sep 2023 14:14:57 -0700
Subject: [PATCH] [NFC][CodeGen] Change CodeGenOpt::{Level,FileType} into enum
classes
This will make it easy for callers to see issues with and fix up calls
to createTargetMachine after a future change to the params of
TargetMachine.
This matches other enums in the CodeGenOpt namespace.
For downstream users, this should be a fairly straightforward replacement,
e.g. s/CodeGenOpt::Aggressive/CodeGenOpt::Level::Aggressive
or s/CodeGenOpt::CGFT_Null/CodeGenOpt::FileType::Null
---
clang/lib/CodeGen/BackendUtil.cpp | 6 +-
clang/lib/Frontend/CompilerInvocation.cpp | 12 ++--
clang/lib/Interpreter/DeviceOffload.cpp | 2 +-
.../clang-fuzzer/handle-llvm/handle_llvm.cpp | 15 +++--
.../ClangLinkerWrapper.cpp | 8 ++-
flang/lib/Frontend/CompilerInvocation.cpp | 4 +-
flang/lib/Frontend/FrontendActions.cpp | 7 +-
lld/ELF/LTO.cpp | 2 +-
lld/MachO/Config.h | 2 +-
lld/wasm/Config.h | 2 +-
lldb/source/Expression/IRExecutionUnit.cpp | 2 +-
llvm/docs/OptBisect.rst | 2 +-
.../MyFirstLanguageFrontend/LangImpl08.rst | 2 +-
llvm/examples/Kaleidoscope/Chapter8/toy.cpp | 2 +-
.../include/llvm/CodeGen/CodeGenPassBuilder.h | 33 +++++-----
.../llvm/CodeGen/GlobalISel/IRTranslator.h | 2 +-
.../CodeGen/GlobalISel/InstructionSelect.h | 2 +-
.../llvm/CodeGen/LinkAllCodegenComponents.h | 22 ++++---
llvm/include/llvm/CodeGen/ParallelCG.h | 3 +-
llvm/include/llvm/CodeGen/SelectionDAGISel.h | 2 +-
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 2 +-
.../llvm/CodeGen/TargetSubtargetInfo.h | 2 +-
.../llvm/ExecutionEngine/ExecutionEngine.h | 2 +-
.../Orc/JITTargetMachineBuilder.h | 2 +-
llvm/include/llvm/LTO/Config.h | 4 +-
.../llvm/LTO/legacy/LTOCodeGenerator.h | 2 +-
.../llvm/LTO/legacy/ThinLTOCodeGenerator.h | 2 +-
llvm/include/llvm/MC/TargetRegistry.h | 12 ++--
llvm/include/llvm/Support/CodeGen.h | 10 +--
llvm/include/llvm/Target/TargetMachine.h | 2 +-
llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | 4 +-
llvm/lib/CodeGen/CommandFlags.cpp | 14 ++--
llvm/lib/CodeGen/DwarfEHPrepare.cpp | 9 +--
llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp | 2 +-
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 9 +--
.../CodeGen/GlobalISel/InstructionSelect.cpp | 8 +--
llvm/lib/CodeGen/LLVMTargetMachine.cpp | 8 +--
llvm/lib/CodeGen/MachineBlockPlacement.cpp | 4 +-
llvm/lib/CodeGen/MachineFunction.cpp | 2 +-
llvm/lib/CodeGen/PrologEpilogInserter.cpp | 4 +-
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 24 +++----
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 3 +-
.../SelectionDAG/SelectionDAGBuilder.cpp | 13 ++--
.../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 46 ++++++-------
llvm/lib/CodeGen/SwitchLoweringUtils.cpp | 4 +-
llvm/lib/CodeGen/TargetPassConfig.cpp | 36 +++++-----
.../lib/CodeGen/TwoAddressInstructionPass.cpp | 8 +--
llvm/lib/ExecutionEngine/ExecutionEngine.cpp | 2 +-
.../Orc/JITTargetMachineBuilder.cpp | 8 +--
llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 4 +-
llvm/lib/LTO/LTO.cpp | 4 +-
llvm/lib/LTO/LTOCodeGenerator.cpp | 5 +-
llvm/lib/LTO/ThinLTOCodeGenerator.cpp | 2 +-
llvm/lib/Target/AArch64/AArch64FastISel.cpp | 2 +-
.../Target/AArch64/AArch64ISelLowering.cpp | 10 +--
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 2 +-
.../Target/AArch64/AArch64TargetMachine.cpp | 66 ++++++++++---------
.../GISel/AArch64PostLegalizerCombiner.cpp | 4 +-
.../GISel/AArch64PreLegalizerCombiner.cpp | 4 +-
.../AMDGPU/AMDGPUInstructionSelector.cpp | 2 +-
.../AMDGPU/AMDGPUPostLegalizerCombiner.cpp | 4 +-
.../AMDGPU/AMDGPUPreLegalizerCombiner.cpp | 4 +-
.../Target/AMDGPU/AMDGPURegBankCombiner.cpp | 4 +-
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 44 ++++++-------
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h | 5 +-
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 2 +-
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 6 +-
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 2 +-
llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 4 +-
llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 6 +-
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp | 4 +-
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 2 +-
llvm/lib/Target/ARM/ARMISelLowering.cpp | 6 +-
llvm/lib/Target/ARM/ARMTargetMachine.cpp | 31 ++++-----
llvm/lib/Target/BPF/BPFTargetMachine.cpp | 2 +-
.../Target/DirectX/DirectXTargetMachine.cpp | 6 +-
.../Target/Hexagon/HexagonCopyToCombine.cpp | 2 +-
.../Target/Hexagon/HexagonFrameLowering.cpp | 8 +--
llvm/lib/Target/Hexagon/HexagonSubtarget.cpp | 2 +-
.../Target/Hexagon/HexagonTargetMachine.cpp | 16 ++---
.../LoongArch/LoongArchTargetMachine.cpp | 2 +-
llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp | 2 +-
llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp | 3 +-
.../Target/Mips/MipsPostLegalizerCombiner.cpp | 4 +-
llvm/lib/Target/Mips/MipsSubtarget.cpp | 2 +-
llvm/lib/Target/Mips/MipsTargetMachine.cpp | 2 +-
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 2 +-
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 10 +--
llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp | 10 +--
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 8 +--
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 +-
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 3 +-
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 34 +++++-----
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 14 ++--
.../Target/SystemZ/SystemZTargetMachine.cpp | 14 ++--
llvm/lib/Target/TargetMachineC.cpp | 12 ++--
.../WebAssembly/WebAssemblyTargetMachine.cpp | 8 +--
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 7 +-
llvm/lib/Target/X86/X86ISelLowering.cpp | 2 +-
llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp | 2 +-
llvm/lib/Target/X86/X86LowerAMXType.cpp | 4 +-
llvm/lib/Target/X86/X86PreAMXConfig.cpp | 2 +-
...culativeExecutionSideEffectSuppression.cpp | 3 +-
llvm/lib/Target/X86/X86TargetMachine.cpp | 14 ++--
llvm/tools/gold/gold-plugin.cpp | 2 +-
llvm/tools/llc/llc.cpp | 17 ++---
llvm/tools/llvm-exegesis/lib/Assembler.cpp | 3 +-
.../llvm-isel-fuzzer/llvm-isel-fuzzer.cpp | 2 +-
.../tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp | 2 +-
llvm/tools/llvm-reduce/ReducerWorkItem.cpp | 2 +-
.../CodeGen/AArch64SelectionDAGTest.cpp | 4 +-
llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp | 2 +-
.../CodeGen/GlobalISel/GISelMITest.cpp | 4 +-
llvm/unittests/CodeGen/InstrRefLDVTest.cpp | 2 +-
llvm/unittests/CodeGen/MFCommon.inc | 2 +-
.../SelectionDAGAddressAnalysisTest.cpp | 4 +-
llvm/unittests/CodeGen/TargetOptionsTest.cpp | 2 +-
.../ExecutionEngine/MCJIT/MCJITTestBase.h | 16 ++---
.../Orc/JITTargetMachineBuilderTest.cpp | 2 +-
llvm/unittests/MI/LiveIntervalTest.cpp | 2 +-
.../AArch64/AArch64SVESchedPseudoTest.cpp | 3 +-
.../Target/AArch64/AddressingModes.cpp | 2 +-
llvm/unittests/Target/AArch64/InstSizes.cpp | 3 +-
.../Target/AArch64/MatrixRegisterAliasing.cpp | 3 +-
llvm/unittests/Target/ARM/InstSizes.cpp | 2 +-
.../unittests/Target/ARM/MachineInstrTest.cpp | 12 ++--
llvm/unittests/Target/LoongArch/InstSizes.cpp | 3 +-
.../Target/PowerPC/AIXRelocModelTest.cpp | 2 +-
.../WebAssemblyExceptionInfoTest.cpp | 3 +-
.../Target/X86/MachineSizeOptsTest.cpp | 3 +-
llvm/unittests/Target/X86/TernlogTest.cpp | 3 +-
.../GPU/Transforms/SerializeToBlob.cpp | 2 +-
mlir/lib/Target/LLVM/ModuleToObject.cpp | 2 +-
.../common/PluginInterface/JIT.cpp | 3 +-
134 files changed, 487 insertions(+), 440 deletions(-)
diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp
index 04cb9064dc789a3..fe3e3136a44cd7c 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -314,12 +314,12 @@ getCodeModel(const CodeGenOptions &CodeGenOpts) {
static CodeGenFileType getCodeGenFileType(BackendAction Action) {
if (Action == Backend_EmitObj)
- return CGFT_ObjectFile;
+ return CodeGenFileType::ObjectFile;
else if (Action == Backend_EmitMCNull)
- return CGFT_Null;
+ return CodeGenFileType::Null;
else {
assert(Action == Backend_EmitAssembly && "Invalid action!");
- return CGFT_AssemblyFile;
+ return CodeGenFileType::AssemblyFile;
}
}
diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp
index 730db8e394f66f1..4782dc5f4c4187d 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -661,27 +661,27 @@ static bool FixupInvocation(CompilerInvocation &Invocation,
static unsigned getOptimizationLevel(ArgList &Args, InputKind IK,
DiagnosticsEngine &Diags) {
- unsigned DefaultOpt = llvm::CodeGenOpt::None;
+ unsigned DefaultOpt = 0;
if ((IK.getLanguage() == Language::OpenCL ||
IK.getLanguage() == Language::OpenCLCXX) &&
!Args.hasArg(OPT_cl_opt_disable))
- DefaultOpt = llvm::CodeGenOpt::Default;
+ DefaultOpt = 2;
if (Arg *A = Args.getLastArg(options::OPT_O_Group)) {
if (A->getOption().matches(options::OPT_O0))
- return llvm::CodeGenOpt::None;
+ return 0;
if (A->getOption().matches(options::OPT_Ofast))
- return llvm::CodeGenOpt::Aggressive;
+ return 3;
assert(A->getOption().matches(options::OPT_O));
StringRef S(A->getValue());
if (S == "s" || S == "z")
- return llvm::CodeGenOpt::Default;
+ return 2;
if (S == "g")
- return llvm::CodeGenOpt::Less;
+ return 1;
return getLastArgIntValue(Args, OPT_O, DefaultOpt, Diags);
}
diff --git a/clang/lib/Interpreter/DeviceOffload.cpp b/clang/lib/Interpreter/DeviceOffload.cpp
index 8e39af6abf9d3d2..fb42964e4936f2d 100644
--- a/clang/lib/Interpreter/DeviceOffload.cpp
+++ b/clang/lib/Interpreter/DeviceOffload.cpp
@@ -88,7 +88,7 @@ llvm::Expected<llvm::StringRef> IncrementalCUDADeviceParser::GeneratePTX() {
llvm::legacy::PassManager PM;
if (TargetMachine->addPassesToEmitFile(PM, dest, nullptr,
- llvm::CGFT_AssemblyFile)) {
+ llvm::CodeGenFileType::AssemblyFile)) {
return llvm::make_error<llvm::StringError>(
"NVPTX backend cannot produce PTX code.",
llvm::inconvertibleErrorCode());
diff --git a/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp b/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp
index bd3490e802e4440..1b3bf0f369e3d3c 100644
--- a/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp
+++ b/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp
@@ -51,7 +51,7 @@ typedef void (*LLVMFunc)(int*, int*, int*, int);
static CodeGenOpt::Level
getOptLevel(const std::vector<const char *> &ExtraArgs) {
// Find the optimization level from the command line args
- CodeGenOpt::Level OLvl = CodeGenOpt::Default;
+ CodeGenOpt::Level OLvl = CodeGenOpt::Level::Default;
for (auto &A : ExtraArgs) {
if (A[0] == '-' && A[1] == 'O') {
if (auto Level = CodeGenOpt::parseLevel(A[2])) {
@@ -76,16 +76,16 @@ static void RunOptimizationPasses(raw_ostream &OS, Module &M,
CodeGenOpt::Level OptLevel) {
llvm::OptimizationLevel OL;
switch (OptLevel) {
- case CodeGenOpt::None:
+ case CodeGenOpt::Level::None:
OL = OptimizationLevel::O0;
break;
- case CodeGenOpt::Less:
+ case CodeGenOpt::Level::Less:
OL = OptimizationLevel::O1;
break;
- case CodeGenOpt::Default:
+ case CodeGenOpt::Level::Default:
OL = OptimizationLevel::O2;
break;
- case CodeGenOpt::Aggressive:
+ case CodeGenOpt::Level::Aggressive:
OL = OptimizationLevel::O3;
break;
}
@@ -205,7 +205,8 @@ static void CreateAndRunJITFunc(const std::string &IR, CodeGenOpt::Level OLvl) {
#endif
// Figure out if we are running the optimized func or the unoptimized func
- RunFuncOnInputs(f, (OLvl == CodeGenOpt::None) ? UnoptArrays : OptArrays);
+ RunFuncOnInputs(f,
+ (OLvl == CodeGenOpt::Level::None) ? UnoptArrays : OptArrays);
EE->runStaticConstructorsDestructors(true);
}
@@ -225,7 +226,7 @@ void clang_fuzzer::HandleLLVM(const std::string &IR,
std::string OptIR = OptLLVM(IR, OLvl);
CreateAndRunJITFunc(OptIR, OLvl);
- CreateAndRunJITFunc(IR, CodeGenOpt::None);
+ CreateAndRunJITFunc(IR, CodeGenOpt::Level::None);
if (memcmp(OptArrays, UnoptArrays, kTotalSize))
ErrorAndExit("!!!BUG!!!");
diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
index 432a34730f923c2..df0d66d240c3266 100644
--- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
+++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
@@ -569,8 +569,9 @@ std::unique_ptr<lto::LTO> createLTO(
};
}
Conf.PostOptModuleHook = Hook;
- Conf.CGFileType =
- (Triple.isNVPTX() || SaveTemps) ? CGFT_AssemblyFile : CGFT_ObjectFile;
+ Conf.CGFileType = (Triple.isNVPTX() || SaveTemps)
+ ? CodeGenFileType::AssemblyFile
+ : CodeGenFileType::ObjectFile;
// TODO: Handle remark files
Conf.HasWholeProgramVisibility = Args.hasArg(OPT_whole_program);
@@ -840,7 +841,8 @@ Expected<StringRef> compileModule(Module &M) {
legacy::PassManager CodeGenPasses;
TargetLibraryInfoImpl TLII(Triple(M.getTargetTriple()));
CodeGenPasses.add(new TargetLibraryInfoWrapperPass(TLII));
- if (TM->addPassesToEmitFile(CodeGenPasses, *OS, nullptr, CGFT_ObjectFile))
+ if (TM->addPassesToEmitFile(CodeGenPasses, *OS, nullptr,
+ CodeGenFileType::ObjectFile))
return createStringError(inconvertibleErrorCode(),
"Failed to execute host backend");
CodeGenPasses.run(M);
diff --git a/flang/lib/Frontend/CompilerInvocation.cpp b/flang/lib/Frontend/CompilerInvocation.cpp
index dba2ac1a335f972..2f46945195be541 100644
--- a/flang/lib/Frontend/CompilerInvocation.cpp
+++ b/flang/lib/Frontend/CompilerInvocation.cpp
@@ -98,12 +98,12 @@ static bool parseShowColorsArgs(const llvm::opt::ArgList &args,
/// Extracts the optimisation level from \a args.
static unsigned getOptimizationLevel(llvm::opt::ArgList &args,
clang::DiagnosticsEngine &diags) {
- unsigned defaultOpt = llvm::CodeGenOpt::None;
+ unsigned defaultOpt = llvm::CodeGenOpt::Level::None;
if (llvm::opt::Arg *a =
args.getLastArg(clang::driver::options::OPT_O_Group)) {
if (a->getOption().matches(clang::driver::options::OPT_O0))
- return llvm::CodeGenOpt::None;
+ return llvm::CodeGenOpt::Level::None;
assert(a->getOption().matches(clang::driver::options::OPT_O));
diff --git a/flang/lib/Frontend/FrontendActions.cpp b/flang/lib/Frontend/FrontendActions.cpp
index 3ca667e64ec25c1..fd7a085dc170858 100644
--- a/flang/lib/Frontend/FrontendActions.cpp
+++ b/flang/lib/Frontend/FrontendActions.cpp
@@ -847,9 +847,10 @@ static void generateMachineCodeOrAssemblyImpl(clang::DiagnosticsEngine &diags,
assert(tlii && "Failed to create TargetLibraryInfo");
codeGenPasses.add(new llvm::TargetLibraryInfoWrapperPass(*tlii));
- llvm::CodeGenFileType cgft = (act == BackendActionTy::Backend_EmitAssembly)
- ? llvm::CodeGenFileType::CGFT_AssemblyFile
- : llvm::CodeGenFileType::CGFT_ObjectFile;
+ llvm::CodeGenFileType cgft =
+ (act == BackendActionTy::Backend_EmitAssembly)
+ ? llvm::CodeGenFileType::CodeGenFileType::AssemblyFile
+ : llvm::CodeGenFileType::CodeGenFileType::ObjectFile;
if (tm.addPassesToEmitFile(codeGenPasses, os, nullptr, cgft)) {
unsigned diagID =
diags.getCustomDiagID(clang::DiagnosticsEngine::Error,
diff --git a/lld/ELF/LTO.cpp b/lld/ELF/LTO.cpp
index e8bfa903726d0ed..1e68d20022c053e 100644
--- a/lld/ELF/LTO.cpp
+++ b/lld/ELF/LTO.cpp
@@ -174,7 +174,7 @@ static lto::Config createConfig() {
}
if (config->ltoEmitAsm) {
- c.CGFileType = CGFT_AssemblyFile;
+ c.CGFileType = CodeGenFileType::AssemblyFile;
c.Options.MCOptions.AsmVerbose = true;
}
diff --git a/lld/MachO/Config.h b/lld/MachO/Config.h
index 3191396f65b832f..388c422b53aebe9 100644
--- a/lld/MachO/Config.h
+++ b/lld/MachO/Config.h
@@ -27,7 +27,7 @@
#include <vector>
namespace llvm::CodeGenOpt {
-enum Level : int;
+enum class Level : int;
} // namespace llvm::CodeGenOpt
namespace lld {
diff --git a/lld/wasm/Config.h b/lld/wasm/Config.h
index 2ca92674d6dc530..247f1b8befc919f 100644
--- a/lld/wasm/Config.h
+++ b/lld/wasm/Config.h
@@ -17,7 +17,7 @@
#include <optional>
namespace llvm::CodeGenOpt {
-enum Level : int;
+enum class Level : int;
} // namespace llvm::CodeGenOpt
namespace lld::wasm {
diff --git a/lldb/source/Expression/IRExecutionUnit.cpp b/lldb/source/Expression/IRExecutionUnit.cpp
index ac9cea7e731f090..fa0ee716169c114 100644
--- a/lldb/source/Expression/IRExecutionUnit.cpp
+++ b/lldb/source/Expression/IRExecutionUnit.cpp
@@ -285,7 +285,7 @@ void IRExecutionUnit::GetRunnableInfo(Status &error, lldb::addr_t &func_addr,
.setRelocationModel(triple.isOSBinFormatMachO() ? llvm::Reloc::PIC_
: llvm::Reloc::Static)
.setMCJITMemoryManager(std::make_unique<MemoryManager>(*this))
- .setOptLevel(llvm::CodeGenOpt::Less);
+ .setOptLevel(llvm::CodeGenOpt::Level::Less);
llvm::StringRef mArch;
llvm::StringRef mCPU;
diff --git a/llvm/docs/OptBisect.rst b/llvm/docs/OptBisect.rst
index a0dc2bd8fdf8060..de32e7177bdb215 100644
--- a/llvm/docs/OptBisect.rst
+++ b/llvm/docs/OptBisect.rst
@@ -19,7 +19,7 @@ skipped while still allowing correct code generation call a function to
check the opt-bisect limit before performing optimizations. Passes which
either must be run or do not modify the IR do not perform this check and are
therefore never skipped. Generally, this means analysis passes, passes
-that are run at CodeGenOpt::None and passes which are required for register
+that are run at CodeGenOpt::Level::None and passes which are required for register
allocation.
The -opt-bisect-limit option can be used with any tool, including front ends
diff --git a/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst b/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst
index 6c7034eb2b84dc4..33ee7d209d4c5d5 100644
--- a/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst
+++ b/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.rst
@@ -155,7 +155,7 @@ pass:
.. code-block:: c++
legacy::PassManager pass;
- auto FileType = CGFT_ObjectFile;
+ auto FileType = CodeGenFileType::ObjectFile;
if (TargetMachine->addPassesToEmitFile(pass, dest, nullptr, FileType)) {
errs() << "TargetMachine can't emit a file of this type";
diff --git a/llvm/examples/Kaleidoscope/Chapter8/toy.cpp b/llvm/examples/Kaleidoscope/Chapter8/toy.cpp
index 3ebc36aa5e899db..1d36a7e67e3d239 100644
--- a/llvm/examples/Kaleidoscope/Chapter8/toy.cpp
+++ b/llvm/examples/Kaleidoscope/Chapter8/toy.cpp
@@ -1258,7 +1258,7 @@ int main() {
}
legacy::PassManager pass;
- auto FileType = CGFT_ObjectFile;
+ auto FileType = CodeGenFileType::ObjectFile;
if (TheTargetMachine->addPassesToEmitFile(pass, dest, nullptr, FileType)) {
errs() << "TheTargetMachine can't emit a file of this type";
diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
index 9236f14a3c86454..878e3166baa9a3d 100644
--- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
@@ -115,7 +115,7 @@ template <typename DerivedT> class CodeGenPassBuilder {
TM.Options.GlobalISelAbort = *Opt.EnableGlobalISelAbort;
if (!Opt.OptimizeRegAlloc)
- Opt.OptimizeRegAlloc = getOptLevel() != CodeGenOpt::None;
+ Opt.OptimizeRegAlloc = getOptLevel() != CodeGenOpt::Level::None;
}
Error buildPipeline(ModulePassManager &MPM, MachineFunctionPassManager &MFPM,
@@ -597,7 +597,7 @@ void CodeGenPassBuilder<Derived>::addIRPasses(AddIRPass &addPass) const {
addPass(VerifierPass());
// Run loop strength reduction before anything else.
- if (getOptLevel() != CodeGenOpt::None && !Opt.DisableLSR) {
+ if (getOptLevel() != CodeGenOpt::Level::None && !Opt.DisableLSR) {
addPass(createFunctionToLoopPassAdaptor(
LoopStrengthReducePass(), /*UseMemorySSA*/ true, Opt.DebugPM));
// FIXME: use -stop-after so we could remove PrintLSR
@@ -605,7 +605,7 @@ void CodeGenPassBuilder<Derived>::addIRPasses(AddIRPass &addPass) const {
addPass(PrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
}
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
// The MergeICmpsPass tries to create memcmp calls by grouping sequences of
// loads and compares. ExpandMemCmpPass then tries to expand those calls
// into optimally-sized loads and compares. The transforms are enabled by a
@@ -625,15 +625,16 @@ void CodeGenPassBuilder<Derived>::addIRPasses(AddIRPass &addPass) const {
addPass(UnreachableBlockElimPass());
// Prepare expensive constants for SelectionDAG.
- if (getOptLevel() != CodeGenOpt::None && !Opt.DisableConstantHoisting)
+ if (getOptLevel() != CodeGenOpt::Level::None && !Opt.DisableConstantHoisting)
addPass(ConstantHoistingPass());
// Replace calls to LLVM intrinsics (e.g., exp, log) operating on vector
// operands with calls to the corresponding functions in a vector library.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(ReplaceWithVeclib());
- if (getOptLevel() != CodeGenOpt::None && !Opt.DisablePartialLibcallInlining)
+ if (getOptLevel() != CodeGenOpt::Level::None &&
+ !Opt.DisablePartialLibcallInlining)
addPass(PartiallyInlineLibCallsPass());
// Instrument function entry and exit, e.g. with calls to mcount().
@@ -648,7 +649,7 @@ void CodeGenPassBuilder<Derived>::addIRPasses(AddIRPass &addPass) const {
addPass(ExpandReductionsPass());
// Convert conditional moves to conditional jumps when profitable.
- if (getOptLevel() != CodeGenOpt::None && !Opt.DisableSelectOptimize)
+ if (getOptLevel() != CodeGenOpt::Level::None && !Opt.DisableSelectOptimize)
addPass(SelectOptimizePass());
}
@@ -702,7 +703,7 @@ void CodeGenPassBuilder<Derived>::addPassesToHandleExceptions(
/// before exception handling preparation passes.
template <typename Derived>
void CodeGenPassBuilder<Derived>::addCodeGenPrepare(AddIRPass &addPass) const {
- if (getOptLevel() != CodeGenOpt::None && !Opt.DisableCGP)
+ if (getOptLevel() != CodeGenOpt::Level::None && !Opt.DisableCGP)
addPass(CodeGenPreparePass());
// TODO: Default ctor'd RewriteSymbolPass is no-op.
// addPass(RewriteSymbolPass());
@@ -748,7 +749,8 @@ Error CodeGenPassBuilder<Derived>::addCoreISelPasses(
(!Opt.EnableGlobalISelOption ||
*Opt.EnableGlobalISelOption == false)))
Selector = SelectorType::GlobalISel;
- else if (TM.getOptLevel() == CodeGenOpt::None && TM.getO0WantsFastISel())
+ else if (TM.getOptLevel() == CodeGenOpt::Level::None &&
+ TM.getO0WantsFastISel())
Selector = SelectorType::FastISel;
else
Selector = SelectorType::SelectionDAG;
@@ -826,7 +828,7 @@ template <typename Derived>
Error CodeGenPassBuilder<Derived>::addMachinePasses(
AddMachinePass &addPass) const {
// Add passes that optimize machine instructions in SSA form.
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
derived().addMachineSSAOptimization(addPass);
} else {
// If the target requests it, assign local variables to stack slots relative
@@ -855,7 +857,7 @@ Error CodeGenPassBuilder<Derived>::addMachinePasses(
addPass(RemoveRedundantDebugValuesPass());
// Insert prolog/epilog code. Eliminate abstract frame index references...
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
addPass(PostRAMachineSinkingPass());
addPass(ShrinkWrapPass());
}
@@ -863,7 +865,7 @@ Error CodeGenPassBuilder<Derived>::addMachinePasses(
addPass(PrologEpilogInserterPass());
/// Add passes that optimize machine instructions after register allocation.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
derived().addMachineLateOptimization(addPass);
// Expand pseudo instructions before second scheduling pass.
@@ -878,7 +880,7 @@ Error CodeGenPassBuilder<Derived>::addMachinePasses(
// Second pass scheduler.
// Let Target optionally insert this pass by itself at some other
// point.
- if (getOptLevel() != CodeGenOpt::None &&
+ if (getOptLevel() != CodeGenOpt::Level::None &&
!TM.targetSchedulesPostRAScheduling()) {
if (Opt.MISchedPostRA)
addPass(PostMachineSchedulerPass());
@@ -890,7 +892,7 @@ Error CodeGenPassBuilder<Derived>::addMachinePasses(
derived().addGCPasses(addPass);
// Basic block placement.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
derived().addBlockPlacement(addPass);
// Insert before XRay Instrumentation.
@@ -912,7 +914,8 @@ Error CodeGenPassBuilder<Derived>::addMachinePasses(
addPass(LiveDebugValuesPass());
addPass(MachineSanitizerBinaryMetadata());
- if (TM.Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None &&
+ if (TM.Options.EnableMachineOutliner &&
+ getOptLevel() != CodeGenOpt::Level::None &&
Opt.EnableMachineOutliner != RunOutliner::NeverOutline) {
bool RunOnAllFunctions =
(Opt.EnableMachineOutliner == RunOutliner::AlwaysOutline);
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
index 0f803bf6c538ea5..616693811600233 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
@@ -716,7 +716,7 @@ class IRTranslator : public MachineFunctionPass {
BranchProbability Prob = BranchProbability::getUnknown());
public:
- IRTranslator(CodeGenOpt::Level OptLevel = CodeGenOpt::None);
+ IRTranslator(CodeGenOpt::Level OptLevel = CodeGenOpt::Level::None);
StringRef getPassName() const override { return "IRTranslator"; }
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelect.h b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelect.h
index 60c7694725a5acf..29bde3b4dafda8c 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelect.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelect.h
@@ -58,7 +58,7 @@ class InstructionSelect : public MachineFunctionPass {
BlockFrequencyInfo *BFI = nullptr;
ProfileSummaryInfo *PSI = nullptr;
- CodeGenOpt::Level OptLevel = CodeGenOpt::None;
+ CodeGenOpt::Level OptLevel = CodeGenOpt::Level::None;
};
} // End namespace llvm.
diff --git a/llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h b/llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h
index 565d1c36d300141..9c7899d80d05e0a 100644
--- a/llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h
+++ b/llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h
@@ -37,16 +37,18 @@ namespace {
(void) llvm::createGreedyRegisterAllocator();
(void) llvm::createDefaultPBQPRegisterAllocator();
- (void) llvm::createBURRListDAGScheduler(nullptr,
- llvm::CodeGenOpt::Default);
- (void) llvm::createSourceListDAGScheduler(nullptr,
- llvm::CodeGenOpt::Default);
- (void) llvm::createHybridListDAGScheduler(nullptr,
- llvm::CodeGenOpt::Default);
- (void) llvm::createFastDAGScheduler(nullptr, llvm::CodeGenOpt::Default);
- (void) llvm::createDefaultScheduler(nullptr, llvm::CodeGenOpt::Default);
- (void) llvm::createVLIWDAGScheduler(nullptr, llvm::CodeGenOpt::Default);
-
+ (void)llvm::createBURRListDAGScheduler(nullptr,
+ llvm::CodeGenOpt::Level::Default);
+ (void)llvm::createSourceListDAGScheduler(
+ nullptr, llvm::CodeGenOpt::Level::Default);
+ (void)llvm::createHybridListDAGScheduler(
+ nullptr, llvm::CodeGenOpt::Level::Default);
+ (void)llvm::createFastDAGScheduler(nullptr,
+ llvm::CodeGenOpt::Level::Default);
+ (void)llvm::createDefaultScheduler(nullptr,
+ llvm::CodeGenOpt::Level::Default);
+ (void)llvm::createVLIWDAGScheduler(nullptr,
+ llvm::CodeGenOpt::Level::Default);
}
} ForceCodegenLinking; // Force link by creating a global definition.
}
diff --git a/llvm/include/llvm/CodeGen/ParallelCG.h b/llvm/include/llvm/CodeGen/ParallelCG.h
index 70ce2ff474213b4..fc50dc1442541bf 100644
--- a/llvm/include/llvm/CodeGen/ParallelCG.h
+++ b/llvm/include/llvm/CodeGen/ParallelCG.h
@@ -36,7 +36,8 @@ void splitCodeGen(
Module &M, ArrayRef<raw_pwrite_stream *> OSs,
ArrayRef<llvm::raw_pwrite_stream *> BCOSs,
const std::function<std::unique_ptr<TargetMachine>()> &TMFactory,
- CodeGenFileType FileType = CGFT_ObjectFile, bool PreserveLocals = false);
+ CodeGenFileType FileType = CodeGenFileType::ObjectFile,
+ bool PreserveLocals = false);
} // namespace llvm
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 0179cf8a1f5925c..fcc9caeb46132d1 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -62,7 +62,7 @@ class SelectionDAGISel : public MachineFunctionPass {
std::unique_ptr<OptimizationRemarkEmitter> ORE;
explicit SelectionDAGISel(char &ID, TargetMachine &tm,
- CodeGenOpt::Level OL = CodeGenOpt::Default);
+ CodeGenOpt::Level OL = CodeGenOpt::Level::Default);
~SelectionDAGISel() override;
const TargetLowering *getTargetLowering() const { return TLI; }
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 1c2ca8678346472..04ecd1d062b5214 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -2109,7 +2109,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// This value will be used if the tail-dup-placement-threshold argument is
/// not provided.
virtual unsigned getTailDuplicateSize(CodeGenOpt::Level OptLevel) const {
- return OptLevel >= CodeGenOpt::Aggressive ? 4 : 2;
+ return OptLevel >= CodeGenOpt::Level::Aggressive ? 4 : 2;
}
/// Returns the callee operand from the given \p MI.
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index 9b98ef353d73ea3..bd78aa0a0bc8b63 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -266,7 +266,7 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
// For use with PostRAScheduling: get the minimum optimization level needed
// to enable post-RA scheduling.
virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
- return CodeGenOpt::Default;
+ return CodeGenOpt::Level::Default;
}
/// True if the subtarget should run the local reassignment
diff --git a/llvm/include/llvm/ExecutionEngine/ExecutionEngine.h b/llvm/include/llvm/ExecutionEngine/ExecutionEngine.h
index 5cd43ffebcdf339..8d0153242c714d5 100644
--- a/llvm/include/llvm/ExecutionEngine/ExecutionEngine.h
+++ b/llvm/include/llvm/ExecutionEngine/ExecutionEngine.h
@@ -586,7 +586,7 @@ class EngineBuilder {
}
/// setOptLevel - Set the optimization level for the JIT. This option
- /// defaults to CodeGenOpt::Default.
+ /// defaults to CodeGenOpt::Level::Default.
EngineBuilder &setOptLevel(CodeGenOpt::Level l) {
OptLevel = l;
return *this;
diff --git a/llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h b/llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h
index 0e72194aec9b1df..a677a5c17da6362 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h
@@ -150,7 +150,7 @@ class JITTargetMachineBuilder {
TargetOptions Options;
std::optional<Reloc::Model> RM;
std::optional<CodeModel::Model> CM;
- CodeGenOpt::Level OptLevel = CodeGenOpt::Default;
+ CodeGenOpt::Level OptLevel = CodeGenOpt::Level::Default;
};
#ifndef NDEBUG
diff --git a/llvm/include/llvm/LTO/Config.h b/llvm/include/llvm/LTO/Config.h
index 5c23ba4f7ac498f..e8f731f8184420b 100644
--- a/llvm/include/llvm/LTO/Config.h
+++ b/llvm/include/llvm/LTO/Config.h
@@ -54,8 +54,8 @@ struct Config {
std::function<void(legacy::PassManager &)> PreCodeGenPassesHook;
std::optional<Reloc::Model> RelocModel = Reloc::PIC_;
std::optional<CodeModel::Model> CodeModel;
- CodeGenOpt::Level CGOptLevel = CodeGenOpt::Default;
- CodeGenFileType CGFileType = CGFT_ObjectFile;
+ CodeGenOpt::Level CGOptLevel = CodeGenOpt::Level::Default;
+ CodeGenFileType CGFileType = CodeGenFileType::ObjectFile;
unsigned OptLevel = 2;
bool VerifyEach = false;
bool DisableVerify = false;
diff --git a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h
index 2093eaa93c85401..07c3046b9e5e54d 100644
--- a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h
+++ b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h
@@ -94,7 +94,7 @@ struct LTOCodeGenerator {
}
/// Set the file type to be emitted (assembly or object code).
- /// The default is CGFT_ObjectFile.
+ /// The default is CodeGenFileType::ObjectFile.
void setFileType(CodeGenFileType FT) { Config.CGFileType = FT; }
void setCpu(StringRef MCpu) { Config.CPU = std::string(MCpu); }
diff --git a/llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h b/llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h
index 37e9b175c452f6e..3aa364275177692 100644
--- a/llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h
+++ b/llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h
@@ -38,7 +38,7 @@ struct TargetMachineBuilder {
std::string MAttr;
TargetOptions Options;
std::optional<Reloc::Model> RelocModel;
- CodeGenOpt::Level CGOptLevel = CodeGenOpt::Aggressive;
+ CodeGenOpt::Level CGOptLevel = CodeGenOpt::Level::Aggressive;
std::unique_ptr<TargetMachine> create() const;
};
diff --git a/llvm/include/llvm/MC/TargetRegistry.h b/llvm/include/llvm/MC/TargetRegistry.h
index 3fa150fc1349cee..f001ae73a2a83cf 100644
--- a/llvm/include/llvm/MC/TargetRegistry.h
+++ b/llvm/include/llvm/MC/TargetRegistry.h
@@ -478,11 +478,13 @@ class Target {
/// feature set; it should always be provided. Generally this should be
/// either the target triple from the module, or the target triple of the
/// host if that does not exist.
- TargetMachine *createTargetMachine(
- StringRef TT, StringRef CPU, StringRef Features,
- const TargetOptions &Options, std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM = std::nullopt,
- CodeGenOpt::Level OL = CodeGenOpt::Default, bool JIT = false) const {
+ TargetMachine *
+ createTargetMachine(StringRef TT, StringRef CPU, StringRef Features,
+ const TargetOptions &Options,
+ std::optional<Reloc::Model> RM,
+ std::optional<CodeModel::Model> CM = std::nullopt,
+ CodeGenOpt::Level OL = CodeGenOpt::Level::Default,
+ bool JIT = false) const {
if (!TargetMachineCtorFn)
return nullptr;
return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM,
diff --git a/llvm/include/llvm/Support/CodeGen.h b/llvm/include/llvm/Support/CodeGen.h
index 7f95bcb9e9d7b94..8b9180c95718ebe 100644
--- a/llvm/include/llvm/Support/CodeGen.h
+++ b/llvm/include/llvm/Support/CodeGen.h
@@ -54,7 +54,7 @@ namespace llvm {
/// Type for the unique integer IDs of code generation optimization levels.
using IDType = int;
/// Code generation optimization level.
- enum Level : IDType {
+ enum class Level : IDType {
None = 0, ///< -O0
Less = 1, ///< -O1
Default = 2, ///< -O2, -Os
@@ -81,10 +81,10 @@ namespace llvm {
/// These enums are meant to be passed into addPassesToEmitFile to indicate
/// what type of file to emit, and returned by it to indicate what type of
/// file could actually be made.
- enum CodeGenFileType {
- CGFT_AssemblyFile,
- CGFT_ObjectFile,
- CGFT_Null // Do not emit any output.
+ enum class CodeGenFileType {
+ AssemblyFile,
+ ObjectFile,
+ Null // Do not emit any output.
};
// Specify what functions should keep the frame pointer.
diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
index 5838758748fa82e..15c33f8d83bbf3a 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -100,7 +100,7 @@ class TargetMachine {
Reloc::Model RM = Reloc::Static;
CodeModel::Model CMModel = CodeModel::Small;
- CodeGenOpt::Level OptLevel = CodeGenOpt::Default;
+ CodeGenOpt::Level OptLevel = CodeGenOpt::Level::Default;
/// Contains target specific asm information.
std::unique_ptr<const MCAsmInfo> AsmInfo;
diff --git a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
index c43ca255505d77c..dc80afd8e350c40 100644
--- a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
@@ -1537,8 +1537,8 @@ void CodeViewDebug::beginFunctionImpl(const MachineFunction *MF) {
}
FPO |= FrameProcedureOptions(uint32_t(CurFn->EncodedLocalFramePtrReg) << 14U);
FPO |= FrameProcedureOptions(uint32_t(CurFn->EncodedParamFramePtrReg) << 16U);
- if (Asm->TM.getOptLevel() != CodeGenOpt::None &&
- !GV.hasOptSize() && !GV.hasOptNone())
+ if (Asm->TM.getOptLevel() != CodeGenOpt::Level::None && !GV.hasOptSize() &&
+ !GV.hasOptNone())
FPO |= FrameProcedureOptions::OptimizedForSpeed;
if (GV.hasProfileData()) {
FPO |= FrameProcedureOptions::ValidProfileCounts;
diff --git a/llvm/lib/CodeGen/CommandFlags.cpp b/llvm/lib/CodeGen/CommandFlags.cpp
index c34a52a6f2de908..59bd6dad3b6ff1d 100644
--- a/llvm/lib/CodeGen/CommandFlags.cpp
+++ b/llvm/lib/CodeGen/CommandFlags.cpp
@@ -180,15 +180,15 @@ codegen::RegisterCodeGenFlags::RegisterCodeGenFlags() {
CGBINDOPT(ExceptionModel);
static cl::opt<CodeGenFileType> FileType(
- "filetype", cl::init(CGFT_AssemblyFile),
+ "filetype", cl::init(CodeGenFileType::AssemblyFile),
cl::desc(
"Choose a file type (not all types are supported by all targets):"),
- cl::values(
- clEnumValN(CGFT_AssemblyFile, "asm", "Emit an assembly ('.s') file"),
- clEnumValN(CGFT_ObjectFile, "obj",
- "Emit a native object ('.o') file"),
- clEnumValN(CGFT_Null, "null",
- "Emit nothing, for performance testing")));
+ cl::values(clEnumValN(CodeGenFileType::AssemblyFile, "asm",
+ "Emit an assembly ('.s') file"),
+ clEnumValN(CodeGenFileType::ObjectFile, "obj",
+ "Emit a native object ('.o') file"),
+ clEnumValN(CodeGenFileType::Null, "null",
+ "Emit nothing, for performance testing")));
CGBINDOPT(FileType);
static cl::opt<FramePointerKind> FramePointerUsage(
diff --git a/llvm/lib/CodeGen/DwarfEHPrepare.cpp b/llvm/lib/CodeGen/DwarfEHPrepare.cpp
index 32c94de7280cb77..2ffa74401f0199d 100644
--- a/llvm/lib/CodeGen/DwarfEHPrepare.cpp
+++ b/llvm/lib/CodeGen/DwarfEHPrepare.cpp
@@ -194,7 +194,7 @@ bool DwarfEHPrepare::InsertUnwindResumeCalls() {
LLVMContext &Ctx = F.getContext();
size_t ResumesLeft = Resumes.size();
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOpt::Level::None) {
ResumesLeft = pruneUnreachableResumes(Resumes, CleanupLPads);
#if LLVM_ENABLE_STATS
unsigned NumRemainingLPs = 0;
@@ -329,7 +329,8 @@ class DwarfEHPrepareLegacyPass : public FunctionPass {
public:
static char ID; // Pass identification, replacement for typeid.
- DwarfEHPrepareLegacyPass(CodeGenOpt::Level OptLevel = CodeGenOpt::Default)
+ DwarfEHPrepareLegacyPass(
+ CodeGenOpt::Level OptLevel = CodeGenOpt::Level::Default)
: FunctionPass(ID), OptLevel(OptLevel) {}
bool runOnFunction(Function &F) override {
@@ -340,7 +341,7 @@ class DwarfEHPrepareLegacyPass : public FunctionPass {
const TargetTransformInfo *TTI = nullptr;
if (auto *DTWP = getAnalysisIfAvailable<DominatorTreeWrapperPass>())
DT = &DTWP->getDomTree();
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOpt::Level::None) {
if (!DT)
DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
TTI = &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
@@ -351,7 +352,7 @@ class DwarfEHPrepareLegacyPass : public FunctionPass {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<TargetPassConfig>();
AU.addRequired<TargetTransformInfoWrapperPass>();
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOpt::Level::None) {
AU.addRequired<DominatorTreeWrapperPass>();
AU.addRequired<TargetTransformInfoWrapperPass>();
}
diff --git a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
index d966fae82985a15..f3d9eda8449137d 100644
--- a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
@@ -78,7 +78,7 @@ bool CSEConfigConstantOnly::shouldCSEOpc(unsigned Opc) {
std::unique_ptr<CSEConfigBase>
llvm::getStandardCSEConfigForOpt(CodeGenOpt::Level Level) {
std::unique_ptr<CSEConfigBase> Config;
- if (Level == CodeGenOpt::None)
+ if (Level == CodeGenOpt::Level::None)
Config = std::make_unique<CSEConfigConstantOnly>();
else
Config = std::make_unique<CSEConfigFull>();
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 41a0295ddbae260..bfcc2e38a6665b7 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -173,7 +173,7 @@ void IRTranslator::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<TargetPassConfig>();
AU.addRequired<GISelCSEAnalysisWrapperPass>();
AU.addRequired<AssumptionCacheTracker>();
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOpt::Level::None) {
AU.addRequired<BranchProbabilityInfoWrapperPass>();
AU.addRequired<AAResultsWrapperPass>();
}
@@ -578,7 +578,8 @@ bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
if (BrInst.isUnconditional()) {
// If the unconditional target is the layout successor, fallthrough.
- if (OptLevel == CodeGenOpt::None || !CurMBB.isLayoutSuccessor(Succ0MBB))
+ if (OptLevel == CodeGenOpt::Level::None ||
+ !CurMBB.isLayoutSuccessor(Succ0MBB))
MIRBuilder.buildBr(*Succ0MBB);
// Link successors.
@@ -1974,7 +1975,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
case Intrinsic::lifetime_start:
case Intrinsic::lifetime_end: {
// No stack colouring in O0, discard region information.
- if (MF->getTarget().getOptLevel() == CodeGenOpt::None)
+ if (MF->getTarget().getOptLevel() == CodeGenOpt::Level::None)
return true;
unsigned Op = ID == Intrinsic::lifetime_start ? TargetOpcode::LIFETIME_START
@@ -3488,7 +3489,7 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
ORE = std::make_unique<OptimizationRemarkEmitter>(&F);
const TargetMachine &TM = MF->getTarget();
TM.resetTargetOptions(F);
- EnableOpts = OptLevel != CodeGenOpt::None && !skipFunction(F);
+ EnableOpts = OptLevel != CodeGenOpt::Level::None && !skipFunction(F);
FuncInfo.MF = MF;
if (EnableOpts) {
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
index 9bbef11067ae78a..ae056f246e38007 100644
--- a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
@@ -65,14 +65,14 @@ InstructionSelect::InstructionSelect(CodeGenOpt::Level OL)
// we use the default opt level here instead of None, so that the addRequired()
// calls are made in getAnalysisUsage().
InstructionSelect::InstructionSelect()
- : MachineFunctionPass(ID), OptLevel(CodeGenOpt::Default) {}
+ : MachineFunctionPass(ID), OptLevel(CodeGenOpt::Level::Default) {}
void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<TargetPassConfig>();
AU.addRequired<GISelKnownBitsAnalysis>();
AU.addPreserved<GISelKnownBitsAnalysis>();
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOpt::Level::None) {
AU.addRequired<ProfileSummaryInfoWrapperPass>();
LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU);
}
@@ -93,11 +93,11 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
CodeGenOpt::Level OldOptLevel = OptLevel;
auto RestoreOptLevel = make_scope_exit([=]() { OptLevel = OldOptLevel; });
- OptLevel = MF.getFunction().hasOptNone() ? CodeGenOpt::None
+ OptLevel = MF.getFunction().hasOptNone() ? CodeGenOpt::Level::None
: MF.getTarget().getOptLevel();
GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOpt::Level::None) {
PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
if (PSI && PSI->hasProfileSummary())
BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp
index d02ec1db1165d41..c7ac17dd877b0ea 100644
--- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp
@@ -156,7 +156,7 @@ Expected<std::unique_ptr<MCStreamer>> LLVMTargetMachine::createMCStreamer(
std::unique_ptr<MCStreamer> AsmStreamer;
switch (FileType) {
- case CGFT_AssemblyFile: {
+ case CodeGenFileType::AssemblyFile: {
MCInstPrinter *InstPrinter = getTarget().createMCInstPrinter(
getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MRI);
@@ -188,7 +188,7 @@ Expected<std::unique_ptr<MCStreamer>> LLVMTargetMachine::createMCStreamer(
AsmStreamer.reset(S);
break;
}
- case CGFT_ObjectFile: {
+ case CodeGenFileType::ObjectFile: {
// Create the code emitter for the target if it exists. If not, .o file
// emission fails.
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, Context);
@@ -211,7 +211,7 @@ Expected<std::unique_ptr<MCStreamer>> LLVMTargetMachine::createMCStreamer(
/*DWARFMustBeAtTheEnd*/ true));
break;
}
- case CGFT_Null:
+ case CodeGenFileType::Null:
// The Null output is intended for use for performance analysis and testing,
// not real users.
AsmStreamer.reset(getTarget().createNullStreamer(Context));
@@ -238,7 +238,7 @@ bool LLVMTargetMachine::addPassesToEmitFile(
return true;
} else {
// MIR printing is redundant with -filetype=null.
- if (FileType != CGFT_Null)
+ if (FileType != CodeGenFileType::Null)
PM.add(createPrintMIRPass(Out));
}
diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
index 912e9ec993e3cc5..14d97810e9127e8 100644
--- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp
+++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
@@ -3376,7 +3376,7 @@ bool MachineBlockPlacement::runOnMachineFunction(MachineFunction &MF) {
TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
// For aggressive optimization, we can adjust some thresholds to be less
// conservative.
- if (PassConfig->getOptLevel() >= CodeGenOpt::Aggressive) {
+ if (PassConfig->getOptLevel() >= CodeGenOpt::Level::Aggressive) {
// At O3 we should be more willing to copy blocks for tail duplication. This
// increases size pressure, so we only do it at O3
// Do this unless only the regular threshold is explicitly set.
@@ -3388,7 +3388,7 @@ bool MachineBlockPlacement::runOnMachineFunction(MachineFunction &MF) {
// If there's no threshold provided through options, query the target
// information for a threshold instead.
if (TailDupPlacementThreshold.getNumOccurrences() == 0 &&
- (PassConfig->getOptLevel() < CodeGenOpt::Aggressive ||
+ (PassConfig->getOptLevel() < CodeGenOpt::Level::Aggressive ||
TailDupPlacementAggressiveThreshold.getNumOccurrences() == 0))
TailDupSize = TII->getTailDuplicateSize(PassConfig->getOptLevel());
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index e1f9488a1c88f34..d8118188dc55879 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -1206,7 +1206,7 @@ bool MachineFunction::shouldUseDebugInstrRef() const {
// have optimized code inlined into this unoptimized code, however with
// fewer and less aggressive optimizations happening, coverage and accuracy
// should not suffer.
- if (getTarget().getOptLevel() == CodeGenOpt::None)
+ if (getTarget().getOptLevel() == CodeGenOpt::Level::None)
return false;
// Don't use instr-ref if this function is marked optnone.
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 6c8be5cff75360e..a4ce92bef152e9d 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -1083,7 +1083,7 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &MF) {
MaxAlign);
// Give the targets a chance to order the objects the way they like it.
- if (MF.getTarget().getOptLevel() != CodeGenOpt::None &&
+ if (MF.getTarget().getOptLevel() != CodeGenOpt::Level::None &&
MF.getTarget().Options.StackSymbolOrdering)
TFI.orderFrameObjects(MF, ObjectsToAllocate);
@@ -1093,7 +1093,7 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &MF) {
// optimizing.
BitVector StackBytesFree;
if (!ObjectsToAllocate.empty() &&
- MF.getTarget().getOptLevel() != CodeGenOpt::None &&
+ MF.getTarget().getOptLevel() != CodeGenOpt::Level::None &&
MFI.getStackProtectorIndex() < 0 && TFI.enableStackSlotScavenging(MF))
computeFreeStackSlots(MFI, StackGrowsDown, MinCSFrameIndex, MaxCSFrameIndex,
FixedCSEnd, StackBytesFree);
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index cd34c0dce0f95a0..ebac425ad2e8525 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2153,7 +2153,7 @@ SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
}
// Don't simplify token factors if optnone.
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOpt::Level::None)
return SDValue();
// Don't simplify the token factor if the node itself has too many operands.
@@ -8789,7 +8789,7 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
// TODO: If there is evidence that running this later would help, this
// limitation could be removed. Legality checks may need to be added
// for the created store and optional bswap/rotate.
- if (LegalOperations || OptLevel == CodeGenOpt::None)
+ if (LegalOperations || OptLevel == CodeGenOpt::Level::None)
return SDValue();
// We only handle merging simple stores of 1-4 bytes.
@@ -18178,7 +18178,7 @@ StoreSDNode *DAGCombiner::getUniqueStoreFeeding(LoadSDNode *LD,
}
SDValue DAGCombiner::ForwardStoreValueToDirectLoad(LoadSDNode *LD) {
- if (OptLevel == CodeGenOpt::None || !LD->isSimple())
+ if (OptLevel == CodeGenOpt::Level::None || !LD->isSimple())
return SDValue();
SDValue Chain = LD->getOperand(0);
int64_t Offset;
@@ -18378,7 +18378,8 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
return V;
// Try to infer better alignment information than the load already has.
- if (OptLevel != CodeGenOpt::None && LD->isUnindexed() && !LD->isAtomic()) {
+ if (OptLevel != CodeGenOpt::Level::None && LD->isUnindexed() &&
+ !LD->isAtomic()) {
if (MaybeAlign Alignment = DAG.InferPtrAlign(Ptr)) {
if (*Alignment > LD->getAlign() &&
isAligned(*Alignment, LD->getSrcValueOffset())) {
@@ -20401,7 +20402,7 @@ bool DAGCombiner::tryStoreMergeOfLoads(SmallVectorImpl<MemOpLink> &StoreNodes,
}
bool DAGCombiner::mergeConsecutiveStores(StoreSDNode *St) {
- if (OptLevel == CodeGenOpt::None || !EnableStoreMerging)
+ if (OptLevel == CodeGenOpt::Level::None || !EnableStoreMerging)
return false;
// TODO: Extend this function to merge stores of scalable vectors.
@@ -20680,7 +20681,8 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
return Chain;
// Try to infer better alignment information than the store already has.
- if (OptLevel != CodeGenOpt::None && ST->isUnindexed() && !ST->isAtomic()) {
+ if (OptLevel != CodeGenOpt::Level::None && ST->isUnindexed() &&
+ !ST->isAtomic()) {
if (MaybeAlign Alignment = DAG.InferPtrAlign(Ptr)) {
if (*Alignment > ST->getAlign() &&
isAligned(*Alignment, ST->getSrcValueOffset())) {
@@ -20796,7 +20798,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) {
if (ST->isUnindexed() && ST->isSimple() &&
ST1->isUnindexed() && ST1->isSimple()) {
- if (OptLevel != CodeGenOpt::None && ST1->getBasePtr() == Ptr &&
+ if (OptLevel != CodeGenOpt::Level::None && ST1->getBasePtr() == Ptr &&
ST1->getValue() == Value && ST->getMemoryVT() == ST1->getMemoryVT() &&
ST->getAddressSpace() == ST1->getAddressSpace()) {
// If this is a store followed by a store with the same value to the
@@ -20804,7 +20806,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
return Chain;
}
- if (OptLevel != CodeGenOpt::None && ST1->hasOneUse() &&
+ if (OptLevel != CodeGenOpt::Level::None && ST1->hasOneUse() &&
!ST1->getBasePtr().isUndef() &&
ST->getAddressSpace() == ST1->getAddressSpace()) {
// If we consider two stores and one smaller in size is a scalable
@@ -20967,7 +20969,7 @@ SDValue DAGCombiner::visitLIFETIME_END(SDNode *N) {
/// }
///
SDValue DAGCombiner::splitMergedValStore(StoreSDNode *ST) {
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOpt::Level::None)
return SDValue();
// Can't change the number of memory accesses for a volatile store or break
@@ -27540,7 +27542,7 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
/// Walk up chain skipping non-aliasing memory nodes, looking for a better chain
/// (aliasing node.)
SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOpt::Level::None)
return OldChain;
// Ops for replacing token factor.
@@ -27697,7 +27699,7 @@ bool DAGCombiner::parallelizeChainedStores(StoreSDNode *St) {
}
bool DAGCombiner::findBetterNeighborChains(StoreSDNode *St) {
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOpt::Level::None)
return false;
const BaseIndexOffset BasePtr = BaseIndexOffset::match(St, DAG);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 8d6d328e8a1f1f6..42d6701ff585ac7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -10291,7 +10291,8 @@ SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
/// For IROrder, we keep the smaller of the two
SDNode *SelectionDAG::UpdateSDLocOnMergeSDNode(SDNode *N, const SDLoc &OLoc) {
DebugLoc NLoc = N->getDebugLoc();
- if (NLoc && OptLevel == CodeGenOpt::None && OLoc.getDebugLoc() != NLoc) {
+ if (NLoc && OptLevel == CodeGenOpt::Level::None &&
+ OLoc.getDebugLoc() != NLoc) {
N->setDebugLoc(DebugLoc());
}
unsigned Order = std::min(N->getIROrder(), OLoc.getIROrder());
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 720fc4944161225..600e0a0be123a42 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -1822,7 +1822,7 @@ void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
// If this is not a fall-through branch or optimizations are switched off,
// emit the branch.
if (TargetMBB != NextBlock(FuncInfo.MBB) ||
- TM.getOptLevel() == CodeGenOpt::None)
+ TM.getOptLevel() == CodeGenOpt::Level::None)
DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
getControlRoot(), DAG.getBasicBlock(TargetMBB)));
return;
@@ -2478,7 +2478,8 @@ void SelectionDAGBuilder::visitBr(const BranchInst &I) {
// If this is not a fall-through branch or optimizations are switched off,
// emit the branch.
- if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None) {
+ if (Succ0MBB != NextBlock(BrMBB) ||
+ TM.getOptLevel() == CodeGenOpt::Level::None) {
auto Br = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
getControlRoot(), DAG.getBasicBlock(Succ0MBB));
setValue(&I, Br);
@@ -7107,7 +7108,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
case Intrinsic::lifetime_end: {
bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
// Stack coloring is not enabled in O0, discard region information.
- if (TM.getOptLevel() == CodeGenOpt::None)
+ if (TM.getOptLevel() == CodeGenOpt::Level::None)
return;
const int64_t ObjectSize =
@@ -11293,7 +11294,7 @@ void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
}
}
- if (TM.getOptLevel() != CodeGenOpt::None) {
+ if (TM.getOptLevel() != CodeGenOpt::Level::None) {
// Here, we order cases by probability so the most likely case will be
// checked first. However, two clusters can have the same probability in
// which case their relative ordering is non-deterministic. So we use Low
@@ -11651,7 +11652,7 @@ MachineBasicBlock *SelectionDAGBuilder::peelDominantCaseCluster(
MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
// Don't perform if there is only one cluster or optimizing for size.
if (SwitchPeelThreshold > 100 || !FuncInfo.BPI || Clusters.size() < 2 ||
- TM.getOptLevel() == CodeGenOpt::None ||
+ TM.getOptLevel() == CodeGenOpt::Level::None ||
SwitchMBB->getParent()->getFunction().hasMinSize())
return SwitchMBB;
@@ -11773,7 +11774,7 @@ void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
SwitchWorkListItem W = WorkList.pop_back_val();
unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
- if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None &&
+ if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::Level::None &&
!DefaultMBB->getParent()->getFunction().hasMinSize()) {
// For optimized builds, lower large range as a balanced binary tree.
splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 91b9d77eed70596..891aa73a30c9cbf 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -225,9 +225,9 @@ namespace llvm {
IS.TM.setOptLevel(NewOptLevel);
LLVM_DEBUG(dbgs() << "\nChanging optimization level for Function "
<< IS.MF->getFunction().getName() << "\n");
- LLVM_DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel << " ; After: -O"
- << NewOptLevel << "\n");
- if (NewOptLevel == CodeGenOpt::None) {
+ LLVM_DEBUG(dbgs() << "\tBefore: -O" << static_cast<int>(SavedOptLevel) << " ; After: -O"
+ << static_cast<int>(NewOptLevel) << "\n");
+ if (NewOptLevel == CodeGenOpt::Level::None) {
IS.TM.setFastISel(IS.TM.getO0WantsFastISel());
LLVM_DEBUG(
dbgs() << "\tFastISel is "
@@ -241,8 +241,8 @@ namespace llvm {
return;
LLVM_DEBUG(dbgs() << "\nRestoring optimization level for Function "
<< IS.MF->getFunction().getName() << "\n");
- LLVM_DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel << " ; After: -O"
- << SavedOptLevel << "\n");
+ LLVM_DEBUG(dbgs() << "\tBefore: -O" << static_cast<int>(IS.OptLevel)
+ << " ; After: -O" << static_cast<int>(SavedOptLevel) << "\n");
IS.OptLevel = SavedOptLevel;
IS.TM.setOptLevel(SavedOptLevel);
IS.TM.setFastISel(SavedFastISel);
@@ -262,7 +262,7 @@ namespace llvm {
return SchedulerCtor(IS, OptLevel);
}
- if (OptLevel == CodeGenOpt::None ||
+ if (OptLevel == CodeGenOpt::Level::None ||
(ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
TLI->getSchedulingPreference() == Sched::Source)
return createSourceListDAGScheduler(IS, OptLevel);
@@ -335,23 +335,23 @@ SelectionDAGISel::~SelectionDAGISel() {
}
void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
- if (OptLevel != CodeGenOpt::None)
- AU.addRequired<AAResultsWrapperPass>();
+ if (OptLevel != CodeGenOpt::Level::None)
+ AU.addRequired<AAResultsWrapperPass>();
AU.addRequired<GCModuleInfo>();
AU.addRequired<StackProtector>();
AU.addPreserved<GCModuleInfo>();
AU.addRequired<TargetLibraryInfoWrapperPass>();
AU.addRequired<TargetTransformInfoWrapperPass>();
AU.addRequired<AssumptionCacheTracker>();
- if (UseMBPI && OptLevel != CodeGenOpt::None)
- AU.addRequired<BranchProbabilityInfoWrapperPass>();
+ if (UseMBPI && OptLevel != CodeGenOpt::Level::None)
+ AU.addRequired<BranchProbabilityInfoWrapperPass>();
AU.addRequired<ProfileSummaryInfoWrapperPass>();
// AssignmentTrackingAnalysis only runs if assignment tracking is enabled for
// the module.
AU.addRequired<AssignmentTrackingAnalysis>();
AU.addPreserved<AssignmentTrackingAnalysis>();
- if (OptLevel != CodeGenOpt::None)
- LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU);
+ if (OptLevel != CodeGenOpt::Level::None)
+ LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU);
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -404,8 +404,8 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
TM.resetTargetOptions(Fn);
// Reset OptLevel to None for optnone functions.
CodeGenOpt::Level NewOptLevel = OptLevel;
- if (OptLevel != CodeGenOpt::None && skipFunction(Fn))
- NewOptLevel = CodeGenOpt::None;
+ if (OptLevel != CodeGenOpt::Level::None && skipFunction(Fn))
+ NewOptLevel = CodeGenOpt::Level::None;
OptLevelChanger OLC(*this, NewOptLevel);
TII = MF->getSubtarget().getInstrInfo();
@@ -417,7 +417,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
AC = &getAnalysis<AssumptionCacheTracker>().getAssumptionCache(mf.getFunction());
auto *PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
BlockFrequencyInfo *BFI = nullptr;
- if (PSI && PSI->hasProfileSummary() && OptLevel != CodeGenOpt::None)
+ if (PSI && PSI->hasProfileSummary() && OptLevel != CodeGenOpt::Level::None)
BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
FunctionVarLocs const *FnVarLocs = nullptr;
@@ -438,12 +438,12 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
// into account). That's unfortunate but OK because it just means we won't
// ask for passes that have been required anyway.
- if (UseMBPI && OptLevel != CodeGenOpt::None)
+ if (UseMBPI && OptLevel != CodeGenOpt::Level::None)
FuncInfo->BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
else
FuncInfo->BPI = nullptr;
- if (OptLevel != CodeGenOpt::None)
+ if (OptLevel != CodeGenOpt::Level::None)
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
else
AA = nullptr;
@@ -456,7 +456,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
// We split CSR if the target supports it for the given function
// and the function has only return exits.
- if (OptLevel != CodeGenOpt::None && TLI->supportSplitCSR(MF)) {
+ if (OptLevel != CodeGenOpt::Level::None && TLI->supportSplitCSR(MF)) {
FuncInfo->SplitCSR = true;
// Collect all the return blocks.
@@ -935,7 +935,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->VerifyDAGDivergence();
#endif
- if (OptLevel != CodeGenOpt::None)
+ if (OptLevel != CodeGenOpt::Level::None)
ComputeLiveOutVRegInfo();
if (ViewISelDAGs && MatchFilterBB)
@@ -1512,7 +1512,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
// Iterate over all basic blocks in the function.
StackProtector &SP = getAnalysis<StackProtector>();
for (const BasicBlock *LLVMBB : RPOT) {
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOpt::Level::None) {
bool AllPredsVisited = true;
for (const BasicBlock *Pred : predecessors(LLVMBB)) {
if (!FuncInfo->VisitedBBs.count(Pred)) {
@@ -2180,7 +2180,8 @@ static bool findNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse,
/// operand node N of U during instruction selection that starts at Root.
bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
SDNode *Root) const {
- if (OptLevel == CodeGenOpt::None) return false;
+ if (OptLevel == CodeGenOpt::Level::None)
+ return false;
return N.hasOneUse();
}
@@ -2189,7 +2190,8 @@ bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
CodeGenOpt::Level OptLevel,
bool IgnoreChains) {
- if (OptLevel == CodeGenOpt::None) return false;
+ if (OptLevel == CodeGenOpt::Level::None)
+ return false;
// If Root use can somehow reach N through a path that doesn't contain
// U then folding N would create a cycle. e.g. In the following
diff --git a/llvm/lib/CodeGen/SwitchLoweringUtils.cpp b/llvm/lib/CodeGen/SwitchLoweringUtils.cpp
index 36a02d5beb4b240..81fbae01ceb43e3 100644
--- a/llvm/lib/CodeGen/SwitchLoweringUtils.cpp
+++ b/llvm/lib/CodeGen/SwitchLoweringUtils.cpp
@@ -95,7 +95,7 @@ void SwitchCG::SwitchLowering::findJumpTables(CaseClusterVector &Clusters,
}
// The algorithm below is not suitable for -O0.
- if (TM->getOptLevel() == CodeGenOpt::None)
+ if (TM->getOptLevel() == CodeGenOpt::Level::None)
return;
// Split Clusters into minimum number of dense partitions. The algorithm uses
@@ -278,7 +278,7 @@ void SwitchCG::SwitchLowering::findBitTestClusters(CaseClusterVector &Clusters,
#endif
// The algorithm below is not suitable for -O0.
- if (TM->getOptLevel() == CodeGenOpt::None)
+ if (TM->getOptLevel() == CodeGenOpt::Level::None)
return;
// If target does not have legal shift left, do not emit bit tests at all.
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 87ac68c834a867e..116e590d6b8630f 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -846,7 +846,7 @@ void TargetPassConfig::addIRPasses() {
if (!DisableVerify)
addPass(createVerifierPass());
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
// Basic AliasAnalysis support.
// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
// BasicAliasAnalysis wins if they disagree. This is intended to help
@@ -889,13 +889,14 @@ void TargetPassConfig::addIRPasses() {
addPass(createUnreachableBlockEliminationPass());
// Prepare expensive constants for SelectionDAG.
- if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
+ if (getOptLevel() != CodeGenOpt::Level::None && !DisableConstantHoisting)
addPass(createConstantHoistingPass());
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(createReplaceWithVeclibLegacyPass());
- if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
+ if (getOptLevel() != CodeGenOpt::Level::None &&
+ !DisablePartialLibcallInlining)
addPass(createPartiallyInlineLibCallsPass());
// Expand vector predication intrinsics into standard IR instructions.
@@ -913,11 +914,11 @@ void TargetPassConfig::addIRPasses() {
if (!DisableExpandReductions)
addPass(createExpandReductionsPass());
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(createTLSVariableHoistPass());
// Convert conditional moves to conditional jumps when profitable.
- if (getOptLevel() != CodeGenOpt::None && !DisableSelectOptimize)
+ if (getOptLevel() != CodeGenOpt::Level::None && !DisableSelectOptimize)
addPass(createSelectOptimizePass());
}
@@ -968,7 +969,7 @@ void TargetPassConfig::addPassesToHandleExceptions() {
/// Add pass to prepare the LLVM IR for code generation. This should be done
/// before exception handling preparation passes.
void TargetPassConfig::addCodeGenPrepare() {
- if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
+ if (getOptLevel() != CodeGenOpt::Level::None && !DisableCGP)
addPass(createCodeGenPreparePass());
}
@@ -1012,7 +1013,8 @@ bool TargetPassConfig::addCoreISelPasses() {
(TM->Options.EnableGlobalISel &&
EnableGlobalISelOption != cl::BOU_FALSE))
Selector = SelectorType::GlobalISel;
- else if (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel())
+ else if (TM->getOptLevel() == CodeGenOpt::Level::None &&
+ TM->getO0WantsFastISel())
Selector = SelectorType::FastISel;
else
Selector = SelectorType::SelectionDAG;
@@ -1129,7 +1131,7 @@ void TargetPassConfig::addMachinePasses() {
AddingMachinePasses = true;
// Add passes that optimize machine instructions in SSA form.
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
addMachineSSAOptimization();
} else {
// If the target requests it, assign local variables to stack slots relative
@@ -1175,7 +1177,7 @@ void TargetPassConfig::addMachinePasses() {
addPass(&FixupStatepointCallerSavedID);
// Insert prolog/epilog code. Eliminate abstract frame index references...
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
addPass(&PostRAMachineSinkingID);
addPass(&ShrinkWrapID);
}
@@ -1186,8 +1188,8 @@ void TargetPassConfig::addMachinePasses() {
addPass(createPrologEpilogInserterPass());
/// Add passes that optimize machine instructions after register allocation.
- if (getOptLevel() != CodeGenOpt::None)
- addMachineLateOptimization();
+ if (getOptLevel() != CodeGenOpt::Level::None)
+ addMachineLateOptimization();
// Expand pseudo instructions before second scheduling pass.
addPass(&ExpandPostRAPseudosID);
@@ -1201,7 +1203,7 @@ void TargetPassConfig::addMachinePasses() {
// Second pass scheduler.
// Let Target optionally insert this pass by itself at some other
// point.
- if (getOptLevel() != CodeGenOpt::None &&
+ if (getOptLevel() != CodeGenOpt::Level::None &&
!TM->targetSchedulesPostRAScheduling()) {
if (MISchedPostRA)
addPass(&PostMachineSchedulerID);
@@ -1216,7 +1218,7 @@ void TargetPassConfig::addMachinePasses() {
}
// Basic block placement.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addBlockPlacement();
// Insert before XRay Instrumentation.
@@ -1240,7 +1242,8 @@ void TargetPassConfig::addMachinePasses() {
addPass(&LiveDebugValuesID);
addPass(&MachineSanitizerBinaryMetadataID);
- if (TM->Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None &&
+ if (TM->Options.EnableMachineOutliner &&
+ getOptLevel() != CodeGenOpt::Level::None &&
EnableMachineOutliner != RunOutliner::NeverOutline) {
bool RunOnAllFunctions =
(EnableMachineOutliner == RunOutliner::AlwaysOutline);
@@ -1344,7 +1347,8 @@ void TargetPassConfig::addMachineSSAOptimization() {
bool TargetPassConfig::getOptimizeRegAlloc() const {
switch (OptimizeRegAlloc) {
- case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
+ case cl::BOU_UNSET:
+ return getOptLevel() != CodeGenOpt::Level::None;
case cl::BOU_TRUE: return true;
case cl::BOU_FALSE: return false;
}
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 45f61262faf9391..a024e4db86fb2b1 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -95,7 +95,7 @@ class TwoAddressInstructionPass : public MachineFunctionPass {
LiveVariables *LV = nullptr;
LiveIntervals *LIS = nullptr;
AliasAnalysis *AA = nullptr;
- CodeGenOpt::Level OptLevel = CodeGenOpt::None;
+ CodeGenOpt::Level OptLevel = CodeGenOpt::Level::None;
// The current basic block being processed.
MachineBasicBlock *MBB = nullptr;
@@ -551,7 +551,7 @@ bool TwoAddressInstructionPass::isProfitableToCommute(Register RegA,
Register RegC,
MachineInstr *MI,
unsigned Dist) {
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOpt::Level::None)
return false;
// Determine if it's profitable to commute this two address instruction. In
@@ -1231,7 +1231,7 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi,
MachineBasicBlock::iterator &nmi,
unsigned SrcIdx, unsigned DstIdx,
unsigned &Dist, bool shouldOnlyCommute) {
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOpt::Level::None)
return false;
MachineInstr &MI = *mi;
@@ -1757,7 +1757,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
// Disable optimizations if requested. We cannot skip the whole pass as some
// fixups are necessary for correctness.
if (skipFunction(Func.getFunction()))
- OptLevel = CodeGenOpt::None;
+ OptLevel = CodeGenOpt::Level::None;
bool MadeChange = false;
diff --git a/llvm/lib/ExecutionEngine/ExecutionEngine.cpp b/llvm/lib/ExecutionEngine/ExecutionEngine.cpp
index 98d7dcb8ec12bd9..f7db2c05d38027a 100644
--- a/llvm/lib/ExecutionEngine/ExecutionEngine.cpp
+++ b/llvm/lib/ExecutionEngine/ExecutionEngine.cpp
@@ -471,7 +471,7 @@ EngineBuilder::EngineBuilder() : EngineBuilder(nullptr) {}
EngineBuilder::EngineBuilder(std::unique_ptr<Module> M)
: M(std::move(M)), WhichEngine(EngineKind::Either), ErrorStr(nullptr),
- OptLevel(CodeGenOpt::Default), MemMgr(nullptr), Resolver(nullptr) {
+ OptLevel(CodeGenOpt::Level::Default), MemMgr(nullptr), Resolver(nullptr) {
// IR module verification is enabled by default in debug builds, and disabled
// by default in release builds.
#ifndef NDEBUG
diff --git a/llvm/lib/ExecutionEngine/Orc/JITTargetMachineBuilder.cpp b/llvm/lib/ExecutionEngine/Orc/JITTargetMachineBuilder.cpp
index b66f52f1ec5d692..26a8706d207526f 100644
--- a/llvm/lib/ExecutionEngine/Orc/JITTargetMachineBuilder.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/JITTargetMachineBuilder.cpp
@@ -126,16 +126,16 @@ void JITTargetMachineBuilderPrinter::print(raw_ostream &OS) const {
OS << "\n"
<< Indent << " Optimization Level = ";
switch (JTMB.OptLevel) {
- case CodeGenOpt::None:
+ case CodeGenOpt::Level::None:
OS << "None";
break;
- case CodeGenOpt::Less:
+ case CodeGenOpt::Level::Less:
OS << "Less";
break;
- case CodeGenOpt::Default:
+ case CodeGenOpt::Level::Default:
OS << "Default";
break;
- case CodeGenOpt::Aggressive:
+ case CodeGenOpt::Level::Aggressive:
OS << "Aggressive";
break;
}
diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
index 6cab70df269c170..d896bee2e71e3c9 100644
--- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
@@ -3344,7 +3344,7 @@ static int32_t computeHeuristicUnrollFactor(CanonicalLoopInfo *CLI) {
// Assume the user requests the most aggressive unrolling, even if the rest of
// the code is optimized using a lower setting.
- CodeGenOpt::Level OptLevel = CodeGenOpt::Aggressive;
+ CodeGenOpt::Level OptLevel = CodeGenOpt::Level::Aggressive;
std::unique_ptr<TargetMachine> TM = createTargetMachine(F, OptLevel);
FunctionAnalysisManager FAM;
@@ -3377,7 +3377,7 @@ static int32_t computeHeuristicUnrollFactor(CanonicalLoopInfo *CLI) {
TargetTransformInfo::UnrollingPreferences UP =
gatherUnrollingPreferences(L, SE, TTI,
/*BlockFrequencyInfo=*/nullptr,
- /*ProfileSummaryInfo=*/nullptr, ORE, OptLevel,
+ /*ProfileSummaryInfo=*/nullptr, ORE, static_cast<int>(OptLevel),
/*UserThreshold=*/std::nullopt,
/*UserCount=*/std::nullopt,
/*UserAllowPartial=*/true,
diff --git a/llvm/lib/LTO/LTO.cpp b/llvm/lib/LTO/LTO.cpp
index 2a3f44d41cbfd1a..3e008edd3ee0b36 100644
--- a/llvm/lib/LTO/LTO.cpp
+++ b/llvm/lib/LTO/LTO.cpp
@@ -142,8 +142,8 @@ void llvm::computeLTOCacheKey(
AddUnsigned(-1);
for (const auto &S : Conf.MllvmArgs)
AddString(S);
- AddUnsigned(Conf.CGOptLevel);
- AddUnsigned(Conf.CGFileType);
+ AddUnsigned(static_cast<int>(Conf.CGOptLevel));
+ AddUnsigned(static_cast<int>(Conf.CGFileType));
AddUnsigned(Conf.OptLevel);
AddUnsigned(Conf.Freestanding);
AddString(Conf.OptPipeline);
diff --git a/llvm/lib/LTO/LTOCodeGenerator.cpp b/llvm/lib/LTO/LTOCodeGenerator.cpp
index 1402da7fbbd2774..a3dab9cc5afdda7 100644
--- a/llvm/lib/LTO/LTOCodeGenerator.cpp
+++ b/llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -306,7 +306,7 @@ bool LTOCodeGenerator::runAIXSystemAssembler(SmallString<128> &AssemblyFile) {
bool LTOCodeGenerator::compileOptimizedToFile(const char **Name) {
if (useAIXSystemAssembler())
- setFileType(CGFT_AssemblyFile);
+ setFileType(CodeGenFileType::AssemblyFile);
// make unique temp output file to put generated code
SmallString<128> Filename;
@@ -314,7 +314,8 @@ bool LTOCodeGenerator::compileOptimizedToFile(const char **Name) {
auto AddStream =
[&](size_t Task,
const Twine &ModuleName) -> std::unique_ptr<CachedFileStream> {
- StringRef Extension(Config.CGFileType == CGFT_AssemblyFile ? "s" : "o");
+ StringRef Extension(
+ Config.CGFileType == CodeGenFileType::AssemblyFile ? "s" : "o");
int FD;
std::error_code EC =
diff --git a/llvm/lib/LTO/ThinLTOCodeGenerator.cpp b/llvm/lib/LTO/ThinLTOCodeGenerator.cpp
index f207b279ac09c66..02a45351462da66 100644
--- a/llvm/lib/LTO/ThinLTOCodeGenerator.cpp
+++ b/llvm/lib/LTO/ThinLTOCodeGenerator.cpp
@@ -338,7 +338,7 @@ std::unique_ptr<MemoryBuffer> codegenModule(Module &TheModule,
PM.add(createObjCARCContractPass());
// Setup the codegen now.
- if (TM.addPassesToEmitFile(PM, OS, nullptr, CGFT_ObjectFile,
+ if (TM.addPassesToEmitFile(PM, OS, nullptr, CodeGenFileType::ObjectFile,
/* DisableVerify */ true))
report_fatal_error("Failed to setup codegen");
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
index b2c46939e58469a..7b982ce0bf89f84 100644
--- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
@@ -5034,7 +5034,7 @@ bool AArch64FastISel::selectGetElementPtr(const Instruction *I) {
}
bool AArch64FastISel::selectAtomicCmpXchg(const AtomicCmpXchgInst *I) {
- assert(TM.getOptLevel() == CodeGenOpt::None &&
+ assert(TM.getOptLevel() == CodeGenOpt::Level::None &&
"cmpxchg survived AtomicExpand at optlevel > -O0");
auto *RetPairTy = cast<StructType>(I->getType());
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index c65c52e39201ac6..ac48a0fdaffbe8f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -15695,8 +15695,8 @@ bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(const Function &F,
bool AArch64TargetLowering::generateFMAsInMachineCombiner(
EVT VT, CodeGenOpt::Level OptLevel) const {
- return (OptLevel >= CodeGenOpt::Aggressive) && !VT.isScalableVector() &&
- !useSVEForFixedLengthVectorVT(VT);
+ return (OptLevel >= CodeGenOpt::Level::Aggressive) &&
+ !VT.isScalableVector() && !useSVEForFixedLengthVectorVT(VT);
}
const MCPhysReg *
@@ -24414,7 +24414,7 @@ AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
// stack and close enough to the spill slot, this can lead to a situation
// where the monitor always gets cleared and the atomic operation can never
// succeed. So at -O0 lower this operation to a CAS loop.
- if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
+ if (getTargetMachine().getOptLevel() == CodeGenOpt::Level::None)
return AtomicExpansionKind::CmpXChg;
// Using CAS for an atomic load has a better chance of succeeding under high
@@ -24466,7 +24466,7 @@ AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
// where the monitor always gets cleared and the atomic operation can never
// succeed. So at -O0 lower this operation to a CAS loop. Also worthwhile if
// we have a single CAS instruction that can replace the loop.
- if (getTargetMachine().getOptLevel() == CodeGenOpt::None ||
+ if (getTargetMachine().getOptLevel() == CodeGenOpt::Level::None ||
Subtarget->hasLSE())
return AtomicExpansionKind::CmpXChg;
@@ -24484,7 +24484,7 @@ AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR(
// on the stack and close enough to the spill slot, this can lead to a
// situation where the monitor always gets cleared and the atomic operation
// can never succeed. So at -O0 we need a late-expanded pseudo-inst instead.
- if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
+ if (getTargetMachine().getOptLevel() == CodeGenOpt::Level::None)
return AtomicExpansionKind::None;
// 128-bit atomic cmpxchg is weird; AtomicExpand doesn't know how to expand
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 3a18f37e31185d2..eeae1663bdeba33 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -8534,7 +8534,7 @@ bool AArch64InstrInfo::isWhileOpcode(unsigned Opc) const {
unsigned int
AArch64InstrInfo::getTailDuplicateSize(CodeGenOpt::Level OptLevel) const {
- return OptLevel >= CodeGenOpt::Aggressive ? 6 : 2;
+ return OptLevel >= CodeGenOpt::Level::Aggressive ? 6 : 2;
}
unsigned llvm::getBLRCallOpcode(const MachineFunction &MF) {
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 6f7fccdf84fed91..f5c07ddc903d7ed 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -358,7 +358,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
// Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
// MachO/CodeModel::Large, which GlobalISel does not support.
- if (getOptLevel() <= EnableGlobalISelAtO &&
+ if (static_cast<int>(getOptLevel()) <= EnableGlobalISelAtO &&
TT.getArch() != Triple::aarch64_32 &&
TT.getEnvironment() != Triple::GNUILP32 &&
!(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
@@ -469,7 +469,7 @@ class AArch64PassConfig : public TargetPassConfig {
public:
AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
: TargetPassConfig(TM, PM) {
- if (TM.getOptLevel() != CodeGenOpt::None)
+ if (TM.getOptLevel() != CodeGenOpt::Level::None)
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
}
@@ -547,13 +547,14 @@ void AArch64PassConfig::addIRPasses() {
addPass(createAtomicExpandPass());
// Expand any SVE vector library calls that we can't code generate directly.
- if (EnableSVEIntrinsicOpts && TM->getOptLevel() == CodeGenOpt::Aggressive)
+ if (EnableSVEIntrinsicOpts &&
+ TM->getOptLevel() == CodeGenOpt::Level::Aggressive)
addPass(createSVEIntrinsicOptsPass());
// Cmpxchg instructions are often used with a subsequent comparison to
// determine whether it succeeded. We can exploit existing control-flow in
// ldrex/strex loops to simplify this, but it needs tidying up.
- if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
+ if (TM->getOptLevel() != CodeGenOpt::Level::None && EnableAtomicTidy)
addPass(createCFGSimplificationPass(SimplifyCFGOptions()
.forwardSwitchCondToPhi(true)
.convertSwitchRangeToICmp(true)
@@ -566,14 +567,14 @@ void AArch64PassConfig::addIRPasses() {
//
// Run this before LSR to remove the multiplies involved in computing the
// pointer values N iterations ahead.
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOpt::Level::None) {
if (EnableLoopDataPrefetch)
addPass(createLoopDataPrefetchPass());
if (EnableFalkorHWPFFix)
addPass(createFalkorMarkStridedAccessesPass());
}
- if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
+ if (TM->getOptLevel() == CodeGenOpt::Level::Aggressive && EnableGEPOpt) {
// Call SeparateConstOffsetFromGEP pass to extract constants within indices
// and lower a GEP with multiple indices to either arithmetic operations or
// multiple GEPs with single index.
@@ -588,19 +589,19 @@ void AArch64PassConfig::addIRPasses() {
TargetPassConfig::addIRPasses();
- if (getOptLevel() == CodeGenOpt::Aggressive && EnableSelectOpt)
+ if (getOptLevel() == CodeGenOpt::Level::Aggressive && EnableSelectOpt)
addPass(createSelectOptimizePass());
addPass(createAArch64GlobalsTaggingPass());
addPass(createAArch64StackTaggingPass(
- /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::None));
+ /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::Level::None));
// Match complex arithmetic patterns
- if (TM->getOptLevel() >= CodeGenOpt::Default)
+ if (TM->getOptLevel() >= CodeGenOpt::Level::Default)
addPass(createComplexDeinterleavingPass(TM));
// Match interleaved memory accesses to ldN/stN intrinsics.
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOpt::Level::None) {
addPass(createInterleavedLoadCombinePass());
addPass(createInterleavedAccessPass());
}
@@ -622,16 +623,17 @@ void AArch64PassConfig::addIRPasses() {
bool AArch64PassConfig::addPreISel() {
// Run promote constant before global merge, so that the promoted constants
// get a chance to be merged
- if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
+ if (TM->getOptLevel() != CodeGenOpt::Level::None && EnablePromoteConstant)
addPass(createAArch64PromoteConstantPass());
// FIXME: On AArch64, this depends on the type.
// Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
// and the offset has to be a multiple of the related size in bytes.
- if ((TM->getOptLevel() != CodeGenOpt::None &&
+ if ((TM->getOptLevel() != CodeGenOpt::Level::None &&
EnableGlobalMerge == cl::BOU_UNSET) ||
EnableGlobalMerge == cl::BOU_TRUE) {
- bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
- (EnableGlobalMerge == cl::BOU_UNSET);
+ bool OnlyOptimizeForSize =
+ (TM->getOptLevel() < CodeGenOpt::Level::Aggressive) &&
+ (EnableGlobalMerge == cl::BOU_UNSET);
// Merging of extern globals is enabled by default on non-Mach-O as we
// expect it to be generally either beneficial or harmless. On Mach-O it
@@ -652,7 +654,7 @@ bool AArch64PassConfig::addPreISel() {
}
void AArch64PassConfig::addCodeGenPrepare() {
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(createTypePromotionLegacyPass());
TargetPassConfig::addCodeGenPrepare();
}
@@ -663,7 +665,7 @@ bool AArch64PassConfig::addInstSelector() {
// For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
// references to _TLS_MODULE_BASE_ as possible.
if (TM->getTargetTriple().isOSBinFormatELF() &&
- getOptLevel() != CodeGenOpt::None)
+ getOptLevel() != CodeGenOpt::Level::None)
addPass(createAArch64CleanupLocalDynamicTLSPass());
return false;
@@ -675,7 +677,7 @@ bool AArch64PassConfig::addIRTranslator() {
}
void AArch64PassConfig::addPreLegalizeMachineIR() {
- if (getOptLevel() == CodeGenOpt::None) {
+ if (getOptLevel() == CodeGenOpt::Level::None) {
addPass(createAArch64O0PreLegalizerCombiner());
addPass(new Localizer());
} else {
@@ -692,7 +694,7 @@ bool AArch64PassConfig::addLegalizeMachineIR() {
}
void AArch64PassConfig::addPreRegBankSelect() {
- bool IsOptNone = getOptLevel() == CodeGenOpt::None;
+ bool IsOptNone = getOptLevel() == CodeGenOpt::Level::None;
if (!IsOptNone) {
addPass(createAArch64PostLegalizerCombiner(IsOptNone));
if (EnableGISelLoadStoreOptPostLegal)
@@ -708,7 +710,7 @@ bool AArch64PassConfig::addRegBankSelect() {
bool AArch64PassConfig::addGlobalInstructionSelect() {
addPass(new InstructionSelect(getOptLevel()));
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(createAArch64PostSelectOptimize());
return false;
}
@@ -717,7 +719,7 @@ void AArch64PassConfig::addMachineSSAOptimization() {
// Run default MachineSSAOptimization first.
TargetPassConfig::addMachineSSAOptimization();
- if (TM->getOptLevel() != CodeGenOpt::None)
+ if (TM->getOptLevel() != CodeGenOpt::Level::None)
addPass(createAArch64MIPeepholeOptPass());
}
@@ -735,18 +737,19 @@ bool AArch64PassConfig::addILPOpts() {
if (EnableStPairSuppress)
addPass(createAArch64StorePairSuppressPass());
addPass(createAArch64SIMDInstrOptPass());
- if (TM->getOptLevel() != CodeGenOpt::None)
+ if (TM->getOptLevel() != CodeGenOpt::Level::None)
addPass(createAArch64StackTaggingPreRAPass());
return true;
}
void AArch64PassConfig::addPreRegAlloc() {
// Change dead register definitions to refer to the zero register.
- if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
+ if (TM->getOptLevel() != CodeGenOpt::Level::None &&
+ EnableDeadRegisterElimination)
addPass(createAArch64DeadRegisterDefinitions());
// Use AdvSIMD scalar instructions whenever profitable.
- if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
+ if (TM->getOptLevel() != CodeGenOpt::Level::None && EnableAdvSIMDScalar) {
addPass(createAArch64AdvSIMDScalar());
// The AdvSIMD pass may produce copies that can be rewritten to
// be register coalescer friendly.
@@ -756,10 +759,11 @@ void AArch64PassConfig::addPreRegAlloc() {
void AArch64PassConfig::addPostRegAlloc() {
// Remove redundant copy instructions.
- if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
+ if (TM->getOptLevel() != CodeGenOpt::Level::None &&
+ EnableRedundantCopyElimination)
addPass(createAArch64RedundantCopyEliminationPass());
- if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
+ if (TM->getOptLevel() != CodeGenOpt::Level::None && usingDefaultRegAlloc())
// Improve performance for some FP/SIMD code for A57.
addPass(createAArch64A57FPLoadBalancing());
}
@@ -771,7 +775,7 @@ void AArch64PassConfig::addPreSched2() {
// Expand some pseudo instructions to allow proper scheduling.
addPass(createAArch64ExpandPseudoPass());
// Use load/store pair instructions when possible.
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOpt::Level::None) {
if (EnableLoadStoreOpt)
addPass(createAArch64LoadStoreOptimizationPass());
}
@@ -788,7 +792,7 @@ void AArch64PassConfig::addPreSched2() {
addPass(createAArch64IndirectThunks());
addPass(createAArch64SLSHardeningPass());
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOpt::Level::None) {
if (EnableFalkorHWPFFix)
addPass(createFalkorHWPFFixPass());
}
@@ -798,10 +802,10 @@ void AArch64PassConfig::addPreEmitPass() {
// Machine Block Placement might have created new opportunities when run
// at O3, where the Tail Duplication Threshold is set to 4 instructions.
// Run the load/store optimizer once more.
- if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
+ if (TM->getOptLevel() >= CodeGenOpt::Level::Aggressive && EnableLoadStoreOpt)
addPass(createAArch64LoadStoreOptimizationPass());
- if (TM->getOptLevel() >= CodeGenOpt::Aggressive &&
+ if (TM->getOptLevel() >= CodeGenOpt::Level::Aggressive &&
EnableAArch64CopyPropagation)
addPass(createMachineCopyPropagationPass(true));
@@ -817,7 +821,7 @@ void AArch64PassConfig::addPreEmitPass() {
addPass(createEHContGuardCatchretPass());
}
- if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
+ if (TM->getOptLevel() != CodeGenOpt::Level::None && EnableCollectLOH &&
TM->getTargetTriple().isOSBinFormatMachO())
addPass(createAArch64CollectLOHPass());
}
@@ -828,7 +832,7 @@ void AArch64PassConfig::addPostBBSections() {
if (BranchRelaxation)
addPass(&BranchRelaxationPassID);
- if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
+ if (TM->getOptLevel() != CodeGenOpt::Level::None && EnableCompressJumpTables)
addPass(createAArch64CompressJumpTablesPass());
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index 5e248f568effcb7..4718c395c152657 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -433,8 +433,8 @@ bool AArch64PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
"Expected a legalized function?");
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
- bool EnableOpt =
- MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
+ bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOpt::Level::None &&
+ !skipFunction(F);
const AArch64Subtarget &ST = MF.getSubtarget<AArch64Subtarget>();
const auto *LI = ST.getLegalizerInfo();
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index cf131613802d3a7..2956bff226be462 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -478,8 +478,8 @@ bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
const auto *LI = ST.getLegalizerInfo();
const Function &F = MF.getFunction();
- bool EnableOpt =
- MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
+ bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOpt::Level::None &&
+ !skipFunction(F);
GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
MachineDominatorTree *MDT = &getAnalysis<MachineDominatorTree>();
CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 1bde2f30e377844..e7c34b37abb3708 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1710,7 +1710,7 @@ bool AMDGPUInstructionSelector::selectDSAppendConsume(MachineInstr &MI,
}
bool AMDGPUInstructionSelector::selectSBarrier(MachineInstr &MI) const {
- if (TM.getOptLevel() > CodeGenOpt::None) {
+ if (TM.getOptLevel() > CodeGenOpt::Level::None) {
unsigned WGSize = STI.getFlatWorkGroupSizes(MF->getFunction()).second;
if (WGSize <= STI.getWavefrontSize()) {
MachineBasicBlock *MBB = MI.getParent();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
index 21cf4794921d3fc..d2f4805cdee8dc7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
@@ -469,8 +469,8 @@ bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
return false;
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
- bool EnableOpt =
- MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
+ bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOpt::Level::None &&
+ !skipFunction(F);
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
const AMDGPULegalizerInfo *LI =
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
index 876aa6d2a4cbf2f..0b5099b254f5a26 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
@@ -265,8 +265,8 @@ bool AMDGPUPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
return false;
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
- bool EnableOpt =
- MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
+ bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOpt::Level::None &&
+ !skipFunction(F);
GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
// Enable CSE.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
index b432d51153ad39d..efefd530d84604c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
@@ -443,8 +443,8 @@ bool AMDGPURegBankCombiner::runOnMachineFunction(MachineFunction &MF) {
return false;
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
- bool EnableOpt =
- MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
+ bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOpt::Level::None &&
+ !skipFunction(F);
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 074280b59e82f4b..67915e0922b3848 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -896,7 +896,7 @@ class GCNPassConfig final : public AMDGPUPassConfig {
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
DAG->addMutation(ST.createFillMFMAShadowMutation(DAG->TII));
DAG->addMutation(createIGroupLPDAGMutation());
- if (isPassEnabled(EnableVOPD, CodeGenOpt::Less))
+ if (isPassEnabled(EnableVOPD, CodeGenOpt::Level::Less))
DAG->addMutation(createVOPDPairingMutation());
return DAG;
}
@@ -943,7 +943,7 @@ AMDGPUPassConfig::AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
}
void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
- if (getOptLevel() == CodeGenOpt::Aggressive)
+ if (getOptLevel() == CodeGenOpt::Level::Aggressive)
addPass(createGVNPass());
else
addPass(createEarlyCSEPass());
@@ -998,22 +998,22 @@ void AMDGPUPassConfig::addIRPasses() {
// AMDGPUAttributor infers lack of llvm.amdgcn.lds.kernel.id calls, so run
// after their introduction
- if (TM.getOptLevel() > CodeGenOpt::None)
+ if (TM.getOptLevel() > CodeGenOpt::Level::None)
addPass(createAMDGPUAttributorPass());
- if (TM.getOptLevel() > CodeGenOpt::None)
+ if (TM.getOptLevel() > CodeGenOpt::Level::None)
addPass(createInferAddressSpacesPass());
// Run atomic optimizer before Atomic Expand
if ((TM.getTargetTriple().getArch() == Triple::amdgcn) &&
- (TM.getOptLevel() >= CodeGenOpt::Less) &&
+ (TM.getOptLevel() >= CodeGenOpt::Level::Less) &&
(AMDGPUAtomicOptimizerStrategy != ScanOptions::None)) {
addPass(createAMDGPUAtomicOptimizerPass(AMDGPUAtomicOptimizerStrategy));
}
addPass(createAtomicExpandPass());
- if (TM.getOptLevel() > CodeGenOpt::None) {
+ if (TM.getOptLevel() > CodeGenOpt::Level::None) {
addPass(createAMDGPUPromoteAlloca());
if (isPassEnabled(EnableScalarIRPasses))
@@ -1035,7 +1035,7 @@ void AMDGPUPassConfig::addIRPasses() {
// Try to hoist loop invariant parts of divisions AMDGPUCodeGenPrepare may
// have expanded.
- if (TM.getOptLevel() > CodeGenOpt::Less)
+ if (TM.getOptLevel() > CodeGenOpt::Level::Less)
addPass(createLICMPass());
}
@@ -1081,7 +1081,7 @@ void AMDGPUPassConfig::addCodeGenPrepare() {
}
bool AMDGPUPassConfig::addPreISel() {
- if (TM->getOptLevel() > CodeGenOpt::None)
+ if (TM->getOptLevel() > CodeGenOpt::Level::None)
addPass(createFlattenCFGPass());
return false;
}
@@ -1132,10 +1132,10 @@ ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
bool GCNPassConfig::addPreISel() {
AMDGPUPassConfig::addPreISel();
- if (TM->getOptLevel() > CodeGenOpt::None)
+ if (TM->getOptLevel() > CodeGenOpt::Level::None)
addPass(createAMDGPULateCodeGenPreparePass());
- if (TM->getOptLevel() > CodeGenOpt::None)
+ if (TM->getOptLevel() > CodeGenOpt::Level::None)
addPass(createSinkingPass());
// Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
@@ -1158,7 +1158,7 @@ bool GCNPassConfig::addPreISel() {
}
addPass(createLCSSAPass());
- if (TM->getOptLevel() > CodeGenOpt::Less)
+ if (TM->getOptLevel() > CodeGenOpt::Level::Less)
addPass(&AMDGPUPerfHintAnalysisID);
return false;
@@ -1209,7 +1209,7 @@ bool GCNPassConfig::addIRTranslator() {
}
void GCNPassConfig::addPreLegalizeMachineIR() {
- bool IsOptNone = getOptLevel() == CodeGenOpt::None;
+ bool IsOptNone = getOptLevel() == CodeGenOpt::Level::None;
addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
addPass(new Localizer());
}
@@ -1220,7 +1220,7 @@ bool GCNPassConfig::addLegalizeMachineIR() {
}
void GCNPassConfig::addPreRegBankSelect() {
- bool IsOptNone = getOptLevel() == CodeGenOpt::None;
+ bool IsOptNone = getOptLevel() == CodeGenOpt::Level::None;
addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
}
@@ -1230,7 +1230,7 @@ bool GCNPassConfig::addRegBankSelect() {
}
void GCNPassConfig::addPreGlobalInstructionSelect() {
- bool IsOptNone = getOptLevel() == CodeGenOpt::None;
+ bool IsOptNone = getOptLevel() == CodeGenOpt::Level::None;
addPass(createAMDGPURegBankCombiner(IsOptNone));
}
@@ -1277,7 +1277,7 @@ void GCNPassConfig::addOptimizedRegAlloc() {
// This is not an essential optimization and it has a noticeable impact on
// compilation time, so we only enable it from O2.
- if (TM->getOptLevel() > CodeGenOpt::Less)
+ if (TM->getOptLevel() > CodeGenOpt::Level::Less)
insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
// FIXME: when an instruction has a Killed operand, and the instruction is
@@ -1385,32 +1385,32 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
void GCNPassConfig::addPostRegAlloc() {
addPass(&SIFixVGPRCopiesID);
- if (getOptLevel() > CodeGenOpt::None)
+ if (getOptLevel() > CodeGenOpt::Level::None)
addPass(&SIOptimizeExecMaskingID);
TargetPassConfig::addPostRegAlloc();
}
void GCNPassConfig::addPreSched2() {
- if (TM->getOptLevel() > CodeGenOpt::None)
+ if (TM->getOptLevel() > CodeGenOpt::Level::None)
addPass(createSIShrinkInstructionsPass());
addPass(&SIPostRABundlerID);
}
void GCNPassConfig::addPreEmitPass() {
- if (isPassEnabled(EnableVOPD, CodeGenOpt::Less))
+ if (isPassEnabled(EnableVOPD, CodeGenOpt::Level::Less))
addPass(&GCNCreateVOPDID);
addPass(createSIMemoryLegalizerPass());
addPass(createSIInsertWaitcntsPass());
addPass(createSIModeRegisterPass());
- if (getOptLevel() > CodeGenOpt::None)
+ if (getOptLevel() > CodeGenOpt::Level::None)
addPass(&SIInsertHardClausesID);
addPass(&SILateBranchLoweringPassID);
- if (isPassEnabled(EnableSetWavePriority, CodeGenOpt::Less))
+ if (isPassEnabled(EnableSetWavePriority, CodeGenOpt::Level::Less))
addPass(createAMDGPUSetWavePriorityPass());
- if (getOptLevel() > CodeGenOpt::None)
+ if (getOptLevel() > CodeGenOpt::Level::None)
addPass(&SIPreEmitPeepholeID);
// The hazard recognizer that runs as part of the post-ra scheduler does not
// guarantee to be able handle all hazards correctly. This is because if there
@@ -1422,7 +1422,7 @@ void GCNPassConfig::addPreEmitPass() {
// cases.
addPass(&PostRAHazardRecognizerID);
- if (isPassEnabled(EnableInsertDelayAlu, CodeGenOpt::Less))
+ if (isPassEnabled(EnableInsertDelayAlu, CodeGenOpt::Level::Less))
addPass(&AMDGPUInsertDelayAluID);
addPass(&BranchRelaxationPassID);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index 2426be405a65912..ef2faf23d41f193 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -136,8 +136,9 @@ class AMDGPUPassConfig : public TargetPassConfig {
/// overrides defaults if explicitly used. Otherwise its default will
/// be used given that a pass shall work at an optimization \p Level
/// minimum.
- bool isPassEnabled(const cl::opt<bool> &Opt,
- CodeGenOpt::Level Level = CodeGenOpt::Default) const {
+ bool
+ isPassEnabled(const cl::opt<bool> &Opt,
+ CodeGenOpt::Level Level = CodeGenOpt::Level::Default) const {
if (Opt.getNumOccurrences())
return Opt;
if (TM->getOptLevel() < Level)
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
index db323465c153f6f..5f27df3d6d69122 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -765,7 +765,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
for (auto MI : PHINodes) {
processPHINode(*MI);
}
- if (MF.getTarget().getOptLevel() > CodeGenOpt::None && EnableM0Merge)
+ if (MF.getTarget().getOptLevel() > CodeGenOpt::Level::None && EnableM0Merge)
hoistAndMergeSGPRInits(AMDGPU::M0, *MRI, TRI, *MDT, TII);
SiblingPenalty.clear();
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 777fe76df1151cd..26f799f8b385617 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2346,7 +2346,7 @@ static void reservePrivateMemoryRegs(const TargetMachine &TM,
// Everything live out of a block is spilled with fast regalloc, so it's
// almost certain that spilling will be required.
- if (TM.getOptLevel() == CodeGenOpt::None)
+ if (TM.getOptLevel() == CodeGenOpt::Level::None)
HasStackObjects = true;
// For now assume stack access is needed in any callee functions, so we need
@@ -8498,7 +8498,7 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
return SDValue(DAG.getMachineNode(Opc, DL, Op->getVTList(), Ops), 0);
}
case Intrinsic::amdgcn_s_barrier: {
- if (getTargetMachine().getOptLevel() > CodeGenOpt::None) {
+ if (getTargetMachine().getOptLevel() > CodeGenOpt::Level::None) {
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
unsigned WGSize = ST.getFlatWorkGroupSizes(MF.getFunction()).second;
if (WGSize <= ST.getWavefrontSize())
@@ -12994,7 +12994,7 @@ SDValue SITargetLowering::performClampCombine(SDNode *N,
SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
- if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
+ if (getTargetMachine().getOptLevel() == CodeGenOpt::Level::None)
return SDValue();
switch (N->getOpcode()) {
case ISD::ADD:
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 122060e10ecccaf..9cf4f955120ce1a 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -1824,7 +1824,7 @@ bool SIInsertWaitcnts::runOnMachineFunction(MachineFunction &MF) {
ForceEmitWaitcnt[T] = false;
OptNone = MF.getFunction().hasOptNone() ||
- MF.getTarget().getOptLevel() == CodeGenOpt::None;
+ MF.getTarget().getOptLevel() == CodeGenOpt::Level::None;
HardwareLimits Limits = {};
Limits.VmcntMax = AMDGPU::getVmcntBitMask(IV);
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
index a173adb6c58b59c..3c91beba13a777f 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -848,8 +848,8 @@ bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) {
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
TII = ST.getInstrInfo();
TRI = &TII->getRegisterInfo();
- EnableOptimizeEndCf =
- RemoveRedundantEndcf && MF.getTarget().getOptLevel() > CodeGenOpt::None;
+ EnableOptimizeEndCf = RemoveRedundantEndcf &&
+ MF.getTarget().getOptLevel() > CodeGenOpt::Level::None;
// This doesn't actually need LiveIntervals, but we can preserve them.
LIS = getAnalysisIfAvailable<LiveIntervals>();
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index 41dee3e2c52af06..1cf0294d63b1217 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -136,13 +136,13 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
else if (F.hasOptSize())
// For small size, but speed and debugging illusion preserved
OptimizationGoal = 3;
- else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
+ else if (TM.getOptLevel() == CodeGenOpt::Level::Aggressive)
// Aggressively for speed, small size and debug illusion sacrificed
OptimizationGoal = 2;
- else if (TM.getOptLevel() > CodeGenOpt::None)
+ else if (TM.getOptLevel() > CodeGenOpt::Level::None)
// For speed, but small size and good debug illusion preserved
OptimizationGoal = 1;
- else // TM.getOptLevel() == CodeGenOpt::None
+ else // TM.getOptLevel() == CodeGenOpt::Level::None
// For good debugging, but speed and small size preserved
OptimizationGoal = 5;
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index a6682f0ca162ce4..fadb9fd06c7bb0b 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -343,9 +343,9 @@ LLVM_DUMP_METHOD void ARMConstantIslands::dumpBBs() {
// Align blocks where the previous block does not fall through. This may add
// extra NOP's but they will not be executed. It uses the PrefLoopAlignment as a
-// measure of how much to align, and only runs at CodeGenOpt::Aggressive.
+// measure of how much to align, and only runs at CodeGenOpt::Level::Aggressive.
static bool AlignBlocks(MachineFunction *MF, const ARMSubtarget *STI) {
- if (MF->getTarget().getOptLevel() != CodeGenOpt::Aggressive ||
+ if (MF->getTarget().getOptLevel() != CodeGenOpt::Level::Aggressive ||
MF->getFunction().hasOptSize())
return false;
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index acd2e4b052b65c9..867988618522944 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -499,7 +499,7 @@ void ARMDAGToDAGISel::PreprocessISelDAG() {
/// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
/// least on current ARM implementations) which should be avoidded.
bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOpt::Level::None)
return true;
if (!Subtarget->hasVMLxHazards())
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 56300bdfd494bd1..876ed7f1e7a4373 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1335,7 +1335,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
// On v8, we have particularly efficient implementations of atomic fences
// if they can be combined with nearby atomic loads and stores.
if (!Subtarget->hasAcquireRelease() ||
- getTargetMachine().getOptLevel() == 0) {
+ getTargetMachine().getOptLevel() == CodeGenOpt::Level::None) {
// Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
InsertFencesForAtomic = true;
}
@@ -21316,7 +21316,7 @@ ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
// the stack and close enough to the spill slot, this can lead to a
// situation where the monitor always gets cleared and the atomic operation
// can never succeed. So at -O0 lower this operation to a CAS loop.
- if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
+ if (getTargetMachine().getOptLevel() == CodeGenOpt::Level::None)
return AtomicExpansionKind::CmpXChg;
return AtomicExpansionKind::LLSC;
}
@@ -21340,7 +21340,7 @@ ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
HasAtomicCmpXchg = Subtarget->hasV7Ops();
else
HasAtomicCmpXchg = Subtarget->hasV6Ops();
- if (getTargetMachine().getOptLevel() != 0 && HasAtomicCmpXchg &&
+ if (getTargetMachine().getOptLevel() != CodeGenOpt::Level::None && HasAtomicCmpXchg &&
Size <= (Subtarget->isMClass() ? 32U : 64U))
return AtomicExpansionKind::LLSC;
return AtomicExpansionKind::None;
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 39d8607818f743d..100fcfa587ca196 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -422,7 +422,7 @@ void ARMPassConfig::addIRPasses() {
// Cmpxchg instructions are often used with a subsequent comparison to
// determine whether it succeeded. We can exploit existing control-flow in
// ldrex/strex loops to simplify this, but it needs tidying up.
- if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
+ if (TM->getOptLevel() != CodeGenOpt::Level::None && EnableAtomicTidy)
addPass(createCFGSimplificationPass(
SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
[this](const Function &F) {
@@ -436,15 +436,15 @@ void ARMPassConfig::addIRPasses() {
TargetPassConfig::addIRPasses();
// Run the parallel DSP pass.
- if (getOptLevel() == CodeGenOpt::Aggressive)
+ if (getOptLevel() == CodeGenOpt::Level::Aggressive)
addPass(createARMParallelDSPPass());
// Match complex arithmetic patterns
- if (TM->getOptLevel() >= CodeGenOpt::Default)
+ if (TM->getOptLevel() >= CodeGenOpt::Level::Default)
addPass(createComplexDeinterleavingPass(TM));
// Match interleaved memory accesses to ldN/stN intrinsics.
- if (TM->getOptLevel() != CodeGenOpt::None)
+ if (TM->getOptLevel() != CodeGenOpt::Level::None)
addPass(createInterleavedAccessPass());
// Add Control Flow Guard checks.
@@ -456,13 +456,13 @@ void ARMPassConfig::addIRPasses() {
}
void ARMPassConfig::addCodeGenPrepare() {
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(createTypePromotionLegacyPass());
TargetPassConfig::addCodeGenPrepare();
}
bool ARMPassConfig::addPreISel() {
- if ((TM->getOptLevel() != CodeGenOpt::None &&
+ if ((TM->getOptLevel() != CodeGenOpt::Level::None &&
EnableGlobalMerge == cl::BOU_UNSET) ||
EnableGlobalMerge == cl::BOU_TRUE) {
// FIXME: This is using the thumb1 only constant value for
@@ -470,8 +470,9 @@ bool ARMPassConfig::addPreISel() {
// to look into using the old value for non-thumb1 code of
// 4095 based on the TargetMachine, but this starts to become
// tricky when doing code gen per function.
- bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
- (EnableGlobalMerge == cl::BOU_UNSET);
+ bool OnlyOptimizeForSize =
+ (TM->getOptLevel() < CodeGenOpt::Level::Aggressive) &&
+ (EnableGlobalMerge == cl::BOU_UNSET);
// Merging of extern globals is enabled by default on non-Mach-O as we
// expect it to be generally either beneficial or harmless. On Mach-O it
// is disabled as we emit the .subsections_via_symbols directive which
@@ -481,7 +482,7 @@ bool ARMPassConfig::addPreISel() {
MergeExternalByDefault));
}
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOpt::Level::None) {
addPass(createHardwareLoopsLegacyPass());
addPass(createMVETailPredicationPass());
// FIXME: IR passes can delete address-taken basic blocks, deleting
@@ -523,8 +524,8 @@ bool ARMPassConfig::addGlobalInstructionSelect() {
}
void ARMPassConfig::addPreRegAlloc() {
- if (getOptLevel() != CodeGenOpt::None) {
- if (getOptLevel() == CodeGenOpt::Aggressive)
+ if (getOptLevel() != CodeGenOpt::Level::None) {
+ if (getOptLevel() == CodeGenOpt::Level::Aggressive)
addPass(&MachinePipelinerID);
addPass(createMVETPAndVPTOptimisationsPass());
@@ -540,7 +541,7 @@ void ARMPassConfig::addPreRegAlloc() {
}
void ARMPassConfig::addPreSched2() {
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
if (EnableARMLoadStoreOpt)
addPass(createARMLoadStoreOptimizationPass());
@@ -552,7 +553,7 @@ void ARMPassConfig::addPreSched2() {
// proper scheduling.
addPass(createARMExpandPseudoPass());
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
// When optimising for size, always run the Thumb2SizeReduction pass before
// IfConversion. Otherwise, check whether IT blocks are restricted
// (e.g. in v8, IfConversion depends on Thumb instruction widths)
@@ -569,7 +570,7 @@ void ARMPassConfig::addPreSched2() {
// Add both scheduling passes to give the subtarget an opportunity to pick
// between them.
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
addPass(&PostMachineSchedulerID);
addPass(&PostRASchedulerID);
}
@@ -588,7 +589,7 @@ void ARMPassConfig::addPreEmitPass() {
}));
// Don't optimize barriers or block placement at -O0.
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
addPass(createARMBlockPlacementPass());
addPass(createARMOptimizeBarriersPass());
}
diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp
index 3926885c05a3920..d76d3784b19636f 100644
--- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp
+++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp
@@ -159,7 +159,7 @@ void BPFPassConfig::addMachineSSAOptimization() {
void BPFPassConfig::addPreEmitPass() {
addPass(createBPFMIPreEmitCheckingPass());
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
if (!DisableMIPeephole)
addPass(createBPFMIPreEmitPeepholePass());
}
diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
index 1111bb86e1c14d2..174f3d3a61a81d5 100644
--- a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
+++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
@@ -129,11 +129,11 @@ bool DirectXTargetMachine::addPassesToEmitFile(
PassConfig->addCodeGenPrepare();
switch (FileType) {
- case CGFT_AssemblyFile:
+ case CodeGenFileType::AssemblyFile:
PM.add(createDXILPrettyPrinterPass(Out));
PM.add(createPrintModulePass(Out, "", true));
break;
- case CGFT_ObjectFile:
+ case CodeGenFileType::ObjectFile:
if (TargetPassConfig::willCompleteCodeGenPipeline()) {
PM.add(createDXILEmbedderPass());
// We embed the other DXContainer globals after embedding DXIL so that the
@@ -149,7 +149,7 @@ bool DirectXTargetMachine::addPassesToEmitFile(
} else
PM.add(createDXILWriterPass(Out));
break;
- case CGFT_Null:
+ case CodeGenFileType::Null:
break;
}
return false;
diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
index 033e6737f8bb8eb..62254cedd422b05 100644
--- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -467,7 +467,7 @@ bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
// Combine aggressively (for code size)
ShouldCombineAggressively =
- MF.getTarget().getOptLevel() <= CodeGenOpt::Default;
+ MF.getTarget().getOptLevel() <= CodeGenOpt::Level::Default;
// Disable CONST64 for tiny core since it takes a LD resource.
if (!OptForSize && ST->isTinyCore())
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index 231ac0825ee1d2e..f7cf2f215090a43 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -381,7 +381,7 @@ static bool isRestoreCall(unsigned Opc) {
static inline bool isOptNone(const MachineFunction &MF) {
return MF.getFunction().hasOptNone() ||
- MF.getTarget().getOptLevel() == CodeGenOpt::None;
+ MF.getTarget().getOptLevel() == CodeGenOpt::Level::None;
}
static inline bool isOptSize(const MachineFunction &MF) {
@@ -1156,7 +1156,7 @@ bool HexagonFrameLowering::hasFP(const MachineFunction &MF) const {
// gdb can't break at the start of the function without it. Will remove if
// this turns out to be a gdb bug.
//
- if (MF.getTarget().getOptLevel() == CodeGenOpt::None)
+ if (MF.getTarget().getOptLevel() == CodeGenOpt::Level::None)
return true;
// By default we want to use SP (since it's always there). FP requires
@@ -1269,7 +1269,7 @@ HexagonFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
int Offset = MFI.getObjectOffset(FI);
bool HasAlloca = MFI.hasVarSizedObjects();
bool HasExtraAlign = HRI.hasStackRealignment(MF);
- bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOpt::None;
+ bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOpt::Level::None;
auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
unsigned FrameSize = MFI.getStackSize();
@@ -2584,7 +2584,7 @@ bool HexagonFrameLowering::shouldInlineCSR(const MachineFunction &MF,
if (!hasFP(MF))
return true;
if (!isOptSize(MF) && !isMinSize(MF))
- if (MF.getTarget().getOptLevel() > CodeGenOpt::Default)
+ if (MF.getTarget().getOptLevel() > CodeGenOpt::Level::Default)
return true;
// Check if CSI only has double registers, and if the registers form
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index 8917be1b56261f0..df27b1d938aad59 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -429,7 +429,7 @@ void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) {
/// Enable use of alias analysis during code generation (during MI
/// scheduling, DAGCombine, etc.).
bool HexagonSubtarget::useAA() const {
- if (OptLevel != CodeGenOpt::None)
+ if (OptLevel != CodeGenOpt::Level::None)
return true;
return false;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 9654c9be303fe7b..0f74cf8a04a6acf 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -237,7 +237,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
"v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
TT, CPU, FS, Options, getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small),
- (HexagonNoOpt ? CodeGenOpt::None : OL)),
+ (HexagonNoOpt ? CodeGenOpt::Level::None : OL)),
TLOF(std::make_unique<HexagonTargetObjectFile>()) {
initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
initAsmInfo();
@@ -330,7 +330,7 @@ TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
void HexagonPassConfig::addIRPasses() {
TargetPassConfig::addIRPasses();
- bool NoOpt = (getOptLevel() == CodeGenOpt::None);
+ bool NoOpt = (getOptLevel() == CodeGenOpt::Level::None);
if (!NoOpt) {
if (EnableInstSimplify)
@@ -363,7 +363,7 @@ void HexagonPassConfig::addIRPasses() {
bool HexagonPassConfig::addInstSelector() {
HexagonTargetMachine &TM = getHexagonTargetMachine();
- bool NoOpt = (getOptLevel() == CodeGenOpt::None);
+ bool NoOpt = (getOptLevel() == CodeGenOpt::Level::None);
if (!NoOpt)
addPass(createHexagonOptimizeSZextends());
@@ -401,7 +401,7 @@ bool HexagonPassConfig::addInstSelector() {
}
void HexagonPassConfig::addPreRegAlloc() {
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
if (EnableCExtOpt)
addPass(createHexagonConstExtenders());
if (EnableExpandCondsets)
@@ -411,12 +411,12 @@ void HexagonPassConfig::addPreRegAlloc() {
if (!DisableHardwareLoops)
addPass(createHexagonHardwareLoops());
}
- if (TM->getOptLevel() >= CodeGenOpt::Default)
+ if (TM->getOptLevel() >= CodeGenOpt::Level::Default)
addPass(&MachinePipelinerID);
}
void HexagonPassConfig::addPostRegAlloc() {
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
if (EnableRDFOpt)
addPass(createHexagonRDFOpt());
if (!DisableHexagonCFGOpt)
@@ -428,13 +428,13 @@ void HexagonPassConfig::addPostRegAlloc() {
void HexagonPassConfig::addPreSched2() {
addPass(createHexagonCopyToCombine());
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(&IfConverterID);
addPass(createHexagonSplitConst32AndConst64());
}
void HexagonPassConfig::addPreEmitPass() {
- bool NoOpt = (getOptLevel() == CodeGenOpt::None);
+ bool NoOpt = (getOptLevel() == CodeGenOpt::Level::None);
if (!NoOpt)
addPass(createHexagonNewValueJump());
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
index 46e4a06f6bc0134..9a9b78f3d05a9d3 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
@@ -159,7 +159,7 @@ void LoongArchPassConfig::addIRPasses() {
//
// Run this before LSR to remove the multiplies involved in computing the
// pointer values N iterations ahead.
- if (TM->getOptLevel() != CodeGenOpt::None && EnableLoopDataPrefetch)
+ if (TM->getOptLevel() != CodeGenOpt::Level::None && EnableLoopDataPrefetch)
addPass(createLoopDataPrefetchPass());
addPass(createAtomicExpandPass());
diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
index c400c9a3fc992f9..912e6cc6fcf8e72 100644
--- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
+++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
@@ -324,7 +324,7 @@ INITIALIZE_PASS(M68kDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
bool M68kDAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
SDNode *Root) const {
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOpt::Level::None)
return false;
if (U == Root) {
diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 8aa5f769c903db2..e5cb9cee632ddec 100644
--- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -610,7 +610,8 @@ bool MipsDelaySlotFiller::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
continue;
// Delay slot filling is disabled at -O0, or in microMIPS32R6.
- if (!DisableDelaySlotFiller && (TM->getOptLevel() != CodeGenOpt::None) &&
+ if (!DisableDelaySlotFiller &&
+ (TM->getOptLevel() != CodeGenOpt::Level::None) &&
!(InMicroMipsMode && STI.hasMips32r6())) {
bool Filled = false;
diff --git a/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp b/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp
index 3d970d6ef9a4758..c974351265ab972 100644
--- a/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp
@@ -130,8 +130,8 @@ bool MipsPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
return false;
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
- bool EnableOpt =
- MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
+ bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOpt::Level::None &&
+ !skipFunction(F);
const MipsSubtarget &ST = MF.getSubtarget<MipsSubtarget>();
const MipsLegalizerInfo *LI =
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index 323e611207a2ab6..4939d79e2050d61 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -235,7 +235,7 @@ void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
}
CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
- return CodeGenOpt::Aggressive;
+ return CodeGenOpt::Level::Aggressive;
}
MipsSubtarget &
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
index fe31ab91d0ea3f9..ca61b6b5d91936f 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
@@ -347,7 +347,7 @@ bool MipsPassConfig::addLegalizeMachineIR() {
}
void MipsPassConfig::addPreRegBankSelect() {
- bool IsOptNone = getOptLevel() == CodeGenOpt::None;
+ bool IsOptNone = getOptLevel() == CodeGenOpt::Level::None;
addPass(createMipsPostLegalizeCombiner(IsOptNone));
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index 62991df958daa4c..3f17c0e9bd095e8 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -43,7 +43,7 @@ INITIALIZE_PASS(NVPTXDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
CodeGenOpt::Level OptLevel)
: SelectionDAGISel(ID, tm, OptLevel), TM(tm) {
- doMulWide = (OptLevel > 0);
+ doMulWide = (OptLevel > CodeGenOpt::Level::None);
}
bool NVPTXDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 8b2d91974e23e4a..2cde8157b7c6300 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -4810,7 +4810,7 @@ bool NVPTXTargetLowering::allowFMA(MachineFunction &MF,
return FMAContractLevelOpt > 0;
// Do not contract if we're not optimizing the code.
- if (OptLevel == 0)
+ if (OptLevel == CodeGenOpt::Level::None)
return false;
// Honor TargetOptions flags that explicitly say fusion is okay.
@@ -4852,7 +4852,7 @@ static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
// Since integer multiply-add costs the same as integer multiply
// but is more costly than integer add, do the fusion only when
// the mul is only used in the add.
- if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
+ if (OptLevel == CodeGenOpt::Level::None || VT != MVT::i32 ||
!N0.getNode()->hasOneUse())
return SDValue();
@@ -5043,7 +5043,7 @@ static SDValue PerformREMCombine(SDNode *N,
assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM);
// Don't do anything at less than -O2.
- if (OptLevel < CodeGenOpt::Default)
+ if (OptLevel < CodeGenOpt::Level::Default)
return SDValue();
SelectionDAG &DAG = DCI.DAG;
@@ -5210,7 +5210,7 @@ static SDValue TryMULWIDECombine(SDNode *N,
static SDValue PerformMULCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
CodeGenOpt::Level OptLevel) {
- if (OptLevel > 0) {
+ if (OptLevel > CodeGenOpt::Level::None) {
// Try mul.wide combining at OptLevel > 0
if (SDValue Ret = TryMULWIDECombine(N, DCI))
return Ret;
@@ -5223,7 +5223,7 @@ static SDValue PerformMULCombine(SDNode *N,
static SDValue PerformSHLCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
CodeGenOpt::Level OptLevel) {
- if (OptLevel > 0) {
+ if (OptLevel > CodeGenOpt::Level::None) {
// Try mul.wide combining at OptLevel > 0
if (SDValue Ret = TryMULWIDECombine(N, DCI))
return Ret;
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
index 1892f951ee835c8..95148a0c332660c 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
@@ -310,7 +310,7 @@ NVPTXTargetMachine::getPredicatedAddrSpace(const Value *V) const {
}
void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
- if (getOptLevel() == CodeGenOpt::Aggressive)
+ if (getOptLevel() == CodeGenOpt::Level::Aggressive)
addPass(createGVNPass());
else
addPass(createEarlyCSEPass());
@@ -373,7 +373,7 @@ void NVPTXPassConfig::addIRPasses() {
const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
addPass(createNVVMReflectPass(ST.getSmVersion()));
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(createNVPTXImageOptimizerPass());
addPass(createNVPTXAssignValidGlobalNamesPass());
addPass(createGenericToNVVMLegacyPass());
@@ -381,7 +381,7 @@ void NVPTXPassConfig::addIRPasses() {
// NVPTXLowerArgs is required for correctness and should be run right
// before the address space inference passes.
addPass(createNVPTXLowerArgsPass());
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
addAddressSpaceInferencePasses();
addStraightLineScalarOptimizationPasses();
}
@@ -403,7 +403,7 @@ void NVPTXPassConfig::addIRPasses() {
// %1 = shl %a, 2
//
// but EarlyCSE can do neither of them.
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
addEarlyCSEOrGVNPass();
if (!DisableLoadStoreVectorizer)
addPass(createLoadStoreVectorizerPass());
@@ -434,7 +434,7 @@ void NVPTXPassConfig::addPreRegAlloc() {
void NVPTXPassConfig::addPostRegAlloc() {
addPass(createNVPTXPrologEpilogPass());
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
// NVPTXPrologEpilogPass calculates frame object offset and replace frame
// index with VRFrame register. NVPTXPeephole need to be run after that and
// will replace VRFrame with VRFrameLocal when possible.
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 1c2f562a0b3b6c6..259cb3c9b902c8e 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -756,8 +756,8 @@ static bool isThreadPointerAcquisitionNode(SDValue Base, SelectionDAG *CurDAG) {
static bool canOptimizeTLSDFormToXForm(SelectionDAG *CurDAG, SDValue Base) {
// Do not do this transformation at -O0.
- if (CurDAG->getTarget().getOptLevel() == CodeGenOpt::None)
- return false;
+ if (CurDAG->getTarget().getOptLevel() == CodeGenOpt::Level::None)
+ return false;
// In order to perform this optimization inside tryTLSXForm[Load|Store],
// Base is expected to be an ADD_TLS node.
@@ -4055,7 +4055,7 @@ bool PPCDAGToDAGISel::tryIntCompareInGPR(SDNode *N) {
// This optimization will emit code that assumes 64-bit registers
// so we don't want to run it in 32-bit mode. Also don't run it
// on functions that are not to be optimized.
- if (TM.getOptLevel() == CodeGenOpt::None || !TM.isPPC64())
+ if (TM.getOptLevel() == CodeGenOpt::Level::None || !TM.isPPC64())
return false;
// For POWER10, it is more profitable to use the set boolean extension
@@ -6667,7 +6667,7 @@ void PPCDAGToDAGISel::PreprocessISelDAG() {
/// on the DAG representation.
void PPCDAGToDAGISel::PostprocessISelDAG() {
// Skip peepholes at -O0.
- if (TM.getOptLevel() == CodeGenOpt::None)
+ if (TM.getOptLevel() == CodeGenOpt::Level::None)
return;
PeepholePPC64();
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 95f2243178c8a10..0491dd2b5b7e0ad 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -399,7 +399,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
// MASS transformation for LLVM intrinsics with replicating fast-math flag
// to be consistent to PPCGenScalarMASSEntries pass
- if (TM.getOptLevel() == CodeGenOpt::Aggressive) {
+ if (TM.getOptLevel() == CodeGenOpt::Level::Aggressive) {
setOperationAction(ISD::FSIN , MVT::f64, Custom);
setOperationAction(ISD::FCOS , MVT::f64, Custom);
setOperationAction(ISD::FPOW , MVT::f64, Custom);
@@ -17134,7 +17134,7 @@ bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
/// target-independent logic.
EVT PPCTargetLowering::getOptimalMemOpType(
const MemOp &Op, const AttributeList &FuncAttributes) const {
- if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
+ if (getTargetMachine().getOptLevel() != CodeGenOpt::Level::None) {
// We should use Altivec/VSX loads and stores when available. For unaligned
// addresses, unaligned VSX loads are only fast starting with the P8.
if (Subtarget.hasAltivec() && Op.size() >= 16) {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 6ca68ecdcc773df..edcd08d14cb2a7d 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -763,7 +763,8 @@ bool PPCInstrInfo::getMachineCombinerPatterns(
bool DoRegPressureReduce) const {
// Using the machine combiner in this way is potentially expensive, so
// restrict to when aggressive optimizations are desired.
- if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive)
+ if (Subtarget.getTargetMachine().getOptLevel() !=
+ CodeGenOpt::Level::Aggressive)
return false;
if (getFMAPatterns(Root, Patterns, DoRegPressureReduce))
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index eaef4bf467c0587..e29c2aed0ddcefb 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -209,14 +209,14 @@ static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
FullFS = "+64bit";
}
- if (OL >= CodeGenOpt::Default) {
+ if (OL >= CodeGenOpt::Level::Default) {
if (!FullFS.empty())
FullFS = "+crbits," + FullFS;
else
FullFS = "+crbits";
}
- if (OL != CodeGenOpt::None) {
+ if (OL != CodeGenOpt::Level::None) {
if (!FullFS.empty())
FullFS = "+invariant-function-descriptors," + FullFS;
else
@@ -414,7 +414,7 @@ class PPCPassConfig : public TargetPassConfig {
: TargetPassConfig(TM, PM) {
// At any optimization level above -O0 we use the Machine Scheduler and not
// the default Post RA List Scheduler.
- if (TM.getOptLevel() != CodeGenOpt::None)
+ if (TM.getOptLevel() != CodeGenOpt::Level::None)
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
}
@@ -454,7 +454,7 @@ TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
}
void PPCPassConfig::addIRPasses() {
- if (TM->getOptLevel() != CodeGenOpt::None)
+ if (TM->getOptLevel() != CodeGenOpt::Level::None)
addPass(createPPCBoolRetToIntPass());
addPass(createAtomicExpandPass());
@@ -463,7 +463,7 @@ void PPCPassConfig::addIRPasses() {
// Generate PowerPC target-specific entries for scalar math functions
// that are available in IBM MASS (scalar) library.
- if (TM->getOptLevel() == CodeGenOpt::Aggressive &&
+ if (TM->getOptLevel() == CodeGenOpt::Level::Aggressive &&
EnablePPCGenScalarMASSEntries) {
TM->Options.PPCGenScalarMASSEntries = EnablePPCGenScalarMASSEntries;
addPass(createPPCGenScalarMASSEntriesPass());
@@ -473,7 +473,7 @@ void PPCPassConfig::addIRPasses() {
if (EnablePrefetch.getNumOccurrences() > 0)
addPass(createLoopDataPrefetchPass());
- if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
+ if (TM->getOptLevel() >= CodeGenOpt::Level::Default && EnableGEPOpt) {
// Call SeparateConstOffsetFromGEP pass to extract constants within indices
// and lower a GEP with multiple indices to either arithmetic operations or
// multiple GEPs with single index.
@@ -490,13 +490,13 @@ void PPCPassConfig::addIRPasses() {
}
bool PPCPassConfig::addPreISel() {
- if (MergeStringPool && getOptLevel() != CodeGenOpt::None)
+ if (MergeStringPool && getOptLevel() != CodeGenOpt::Level::None)
addPass(createPPCMergeStringPoolPass());
- if (!DisableInstrFormPrep && getOptLevel() != CodeGenOpt::None)
+ if (!DisableInstrFormPrep && getOptLevel() != CodeGenOpt::Level::None)
addPass(createPPCLoopInstrFormPrepPass(getPPCTargetMachine()));
- if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
+ if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::Level::None)
addPass(createHardwareLoopsLegacyPass());
return false;
@@ -516,7 +516,7 @@ bool PPCPassConfig::addInstSelector() {
addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
#ifndef NDEBUG
- if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
+ if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::Level::None)
addPass(createPPCCTRLoopsVerify());
#endif
@@ -527,12 +527,12 @@ bool PPCPassConfig::addInstSelector() {
void PPCPassConfig::addMachineSSAOptimization() {
// Run CTR loops pass before any cfg modification pass to prevent the
// canonical form of hardware loop from being destroied.
- if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
+ if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::Level::None)
addPass(createPPCCTRLoopsPass());
// PPCBranchCoalescingPass need to be done before machine sinking
// since it merges empty blocks.
- if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
+ if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::Level::None)
addPass(createPPCBranchCoalescingPass());
TargetPassConfig::addMachineSSAOptimization();
// For little endian, remove where possible the vector swap instructions
@@ -541,7 +541,7 @@ void PPCPassConfig::addMachineSSAOptimization() {
!DisableVSXSwapRemoval)
addPass(createPPCVSXSwapRemovalPass());
// Reduce the number of cr-logical ops.
- if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
+ if (ReduceCRLogical && getOptLevel() != CodeGenOpt::Level::None)
addPass(createPPCReduceCRLogicalsPass());
// Target-specific peephole cleanups performed after instruction
// selection.
@@ -552,7 +552,7 @@ void PPCPassConfig::addMachineSSAOptimization() {
}
void PPCPassConfig::addPreRegAlloc() {
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
&PPCVSXFMAMutateID);
@@ -570,12 +570,12 @@ void PPCPassConfig::addPreRegAlloc() {
if (EnableExtraTOCRegDeps)
addPass(createPPCTOCRegDepsPass());
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(&MachinePipelinerID);
}
void PPCPassConfig::addPreSched2() {
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(&IfConverterID);
}
@@ -583,7 +583,7 @@ void PPCPassConfig::addPreEmitPass() {
addPass(createPPCPreEmitPeepholePass());
addPass(createPPCExpandISELPass());
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(createPPCEarlyReturnPass());
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index d4fd66c9b360c4e..a6eedeeae2895a7 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -284,7 +284,7 @@ TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
void RISCVPassConfig::addIRPasses() {
addPass(createAtomicExpandPass());
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
addPass(createRISCVGatherScatterLoweringPass());
addPass(createInterleavedAccessPass());
addPass(createRISCVCodeGenPreparePass());
@@ -294,7 +294,7 @@ void RISCVPassConfig::addIRPasses() {
}
bool RISCVPassConfig::addPreISel() {
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOpt::Level::None) {
// Add a barrier before instruction selection so that we will not get
// deleted block address after enabling default outlining. See D99707 for
// more details.
@@ -350,12 +350,13 @@ void RISCVPassConfig::addPreEmitPass() {
// propagation after the machine outliner (which runs after addPreEmitPass)
// currently leads to incorrect code-gen, where copies to registers within
// outlined functions are removed erroneously.
- if (TM->getOptLevel() >= CodeGenOpt::Default && EnableRISCVCopyPropagation)
+ if (TM->getOptLevel() >= CodeGenOpt::Level::Default &&
+ EnableRISCVCopyPropagation)
addPass(createMachineCopyPropagationPass(true));
}
void RISCVPassConfig::addPreEmitPass2() {
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOpt::Level::None) {
addPass(createRISCVMoveMergePass());
// Schedule PushPop Optimization before expansion of Pseudo instruction,
// ensuring return instruction is detected correctly.
@@ -386,7 +387,7 @@ void RISCVPassConfig::addMachineSSAOptimization() {
void RISCVPassConfig::addPreRegAlloc() {
addPass(createRISCVPreRAExpandPseudoPass());
- if (TM->getOptLevel() != CodeGenOpt::None)
+ if (TM->getOptLevel() != CodeGenOpt::Level::None)
addPass(createRISCVMergeBaseOffsetOptPass());
addPass(createRISCVInsertVSETVLIPass());
addPass(createRISCVInsertReadWriteCSRPass());
@@ -405,7 +406,8 @@ void RISCVPassConfig::addFastRegAlloc() {
void RISCVPassConfig::addPostRegAlloc() {
- if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
+ if (TM->getOptLevel() != CodeGenOpt::Level::None &&
+ EnableRedundantCopyElimination)
addPass(createRISCVRedundantCopyEliminationPass());
}
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
index 787c51645de16d7..7a26be940d52805 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -221,7 +221,7 @@ class SystemZPassConfig : public TargetPassConfig {
} // end anonymous namespace
void SystemZPassConfig::addIRPasses() {
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
addPass(createSystemZTDCPass());
addPass(createLoopDataPrefetchPass());
}
@@ -232,7 +232,7 @@ void SystemZPassConfig::addIRPasses() {
bool SystemZPassConfig::addInstSelector() {
addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(createSystemZLDCleanupPass(getSystemZTargetMachine()));
return false;
@@ -254,12 +254,12 @@ void SystemZPassConfig::addPostRewrite() {
void SystemZPassConfig::addPostRegAlloc() {
// PostRewrite needs to be run at -O0 also (in which case addPostRewrite()
// is not called).
- if (getOptLevel() == CodeGenOpt::None)
+ if (getOptLevel() == CodeGenOpt::Level::None)
addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
}
void SystemZPassConfig::addPreSched2() {
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(&IfConverterID);
}
@@ -267,7 +267,7 @@ void SystemZPassConfig::addPreEmitPass() {
// Do instruction shortening before compare elimination because some
// vector instructions will be shortened into opcodes that compare
// elimination recognizes.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(createSystemZShortenInstPass(getSystemZTargetMachine()));
// We eliminate comparisons here rather than earlier because some
@@ -293,14 +293,14 @@ void SystemZPassConfig::addPreEmitPass() {
// Doing it so late makes it more likely that a register will be reused
// between the comparison and the branch, but it isn't clear whether
// preventing that would be a win or not.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(createSystemZElimComparePass(getSystemZTargetMachine()));
addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
// Do final scheduling after all other optimizations, to get an
// optimal input for the decoder (branch relaxation must happen
// after block placement).
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(&PostMachineSchedulerID);
}
diff --git a/llvm/lib/Target/TargetMachineC.cpp b/llvm/lib/Target/TargetMachineC.cpp
index 7cd29b40da12ce1..4390f090f5b6b5d 100644
--- a/llvm/lib/Target/TargetMachineC.cpp
+++ b/llvm/lib/Target/TargetMachineC.cpp
@@ -130,16 +130,16 @@ LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T,
CodeGenOpt::Level OL;
switch (Level) {
case LLVMCodeGenLevelNone:
- OL = CodeGenOpt::None;
+ OL = CodeGenOpt::Level::None;
break;
case LLVMCodeGenLevelLess:
- OL = CodeGenOpt::Less;
+ OL = CodeGenOpt::Level::Less;
break;
case LLVMCodeGenLevelAggressive:
- OL = CodeGenOpt::Aggressive;
+ OL = CodeGenOpt::Level::Aggressive;
break;
default:
- OL = CodeGenOpt::Default;
+ OL = CodeGenOpt::Level::Default;
break;
}
@@ -195,10 +195,10 @@ static LLVMBool LLVMTargetMachineEmit(LLVMTargetMachineRef T, LLVMModuleRef M,
CodeGenFileType ft;
switch (codegen) {
case LLVMAssemblyFile:
- ft = CGFT_AssemblyFile;
+ ft = CodeGenFileType::AssemblyFile;
break;
default:
- ft = CGFT_ObjectFile;
+ ft = CodeGenFileType::ObjectFile;
break;
}
if (TM->addPassesToEmitFile(pass, OS, nullptr, ft)) {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
index f8a4b95a95515e4..a23e48e37022050 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -426,7 +426,7 @@ void WebAssemblyPassConfig::addIRPasses() {
addPass(createWebAssemblyFixFunctionBitcasts());
// Optimize "returned" function attributes.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(createWebAssemblyOptimizeReturned());
basicCheckForEHAndSjLj(TM);
@@ -503,7 +503,7 @@ void WebAssemblyPassConfig::addOptimizedRegAlloc() {
// usually not used for production builds.
// TODO Investigate why RegisterCoalesce degrades debug info quality and fix
// it properly
- if (getOptLevel() == CodeGenOpt::Less)
+ if (getOptLevel() == CodeGenOpt::Level::Less)
disablePass(&RegisterCoalescerID);
TargetPassConfig::addOptimizedRegAlloc();
}
@@ -550,7 +550,7 @@ void WebAssemblyPassConfig::addPreEmitPass() {
addPass(createWebAssemblyReplacePhysRegs());
// Preparations and optimizations related to register stackification.
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
// Depend on LiveIntervals and perform some optimizations on it.
addPass(createWebAssemblyOptimizeLiveIntervals());
@@ -585,7 +585,7 @@ void WebAssemblyPassConfig::addPreEmitPass() {
addPass(createWebAssemblyLowerBrUnless());
// Perform the very last peephole optimizations on the code.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(createWebAssemblyPeephole());
// Create a mapping from LLVM CodeGen virtual registers to wasm registers.
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index fed26111f60ec65..daa48c69f191549 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -624,7 +624,8 @@ bool X86DAGToDAGISel::isMaskZeroExtended(SDNode *N) const {
bool
X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
- if (OptLevel == CodeGenOpt::None) return false;
+ if (OptLevel == CodeGenOpt::Level::None)
+ return false;
if (!N.hasOneUse())
return false;
@@ -1242,7 +1243,7 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
}
}
- if (OptLevel != CodeGenOpt::None &&
+ if (OptLevel != CodeGenOpt::Level::None &&
// Only do this when the target can fold the load into the call or
// jmp.
!Subtarget->useIndirectThunkCalls() &&
@@ -1481,7 +1482,7 @@ bool X86DAGToDAGISel::tryOptimizeRem8Extend(SDNode *N) {
void X86DAGToDAGISel::PostprocessISelDAG() {
// Skip peepholes at -O0.
- if (TM.getOptLevel() == CodeGenOpt::None)
+ if (TM.getOptLevel() == CodeGenOpt::Level::None)
return;
SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 008e34ae3c7ff37..9e349e60b04994d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -116,7 +116,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
// Bypass expensive divides and use cheaper ones.
- if (TM.getOptLevel() >= CodeGenOpt::Default) {
+ if (TM.getOptLevel() >= CodeGenOpt::Level::Default) {
if (Subtarget.hasSlowDivide32())
addBypassSlowDiv(32, 8);
if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
diff --git a/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp b/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
index 102a8ce56852781..444ea8c00ea97ae 100644
--- a/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
+++ b/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
@@ -646,7 +646,7 @@ class X86LowerAMXIntrinsicsLegacyPass : public FunctionPass {
return false;
TargetMachine *TM = &getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
if (!F.hasFnAttribute(Attribute::OptimizeNone) &&
- TM->getOptLevel() != CodeGenOpt::None)
+ TM->getOptLevel() != CodeGenOpt::Level::None)
return false;
auto *DTWP = getAnalysisIfAvailable<DominatorTreeWrapperPass>();
diff --git a/llvm/lib/Target/X86/X86LowerAMXType.cpp b/llvm/lib/Target/X86/X86LowerAMXType.cpp
index d20d5fe96f492c9..acdec04a52e8e34 100644
--- a/llvm/lib/Target/X86/X86LowerAMXType.cpp
+++ b/llvm/lib/Target/X86/X86LowerAMXType.cpp
@@ -1247,8 +1247,8 @@ class X86LowerAMXTypeLegacyPass : public FunctionPass {
// Prepare for fast register allocation at O0.
// Todo: May better check the volatile model of AMX code, not just
- // by checking Attribute::OptimizeNone and CodeGenOpt::None.
- if (TM->getOptLevel() == CodeGenOpt::None) {
+ // by checking Attribute::OptimizeNone and CodeGenOpt::Level::None.
+ if (TM->getOptLevel() == CodeGenOpt::Level::None) {
// If Front End not use O0 but the Mid/Back end use O0, (e.g.
// "Clang -O2 -S -emit-llvm t.c" + "llc t.ll") we should make
// sure the amx data is volatile, that is nessary for AMX fast
diff --git a/llvm/lib/Target/X86/X86PreAMXConfig.cpp b/llvm/lib/Target/X86/X86PreAMXConfig.cpp
index c9c59af8d6d74b2..a8d8fcba711f225 100644
--- a/llvm/lib/Target/X86/X86PreAMXConfig.cpp
+++ b/llvm/lib/Target/X86/X86PreAMXConfig.cpp
@@ -383,7 +383,7 @@ class X86PreAMXConfigPass : public FunctionPass {
bool C = false;
// Prepare for fast register allocation at O0.
- if (TM->getOptLevel() == CodeGenOpt::None) {
+ if (TM->getOptLevel() == CodeGenOpt::Level::None) {
// We pre-config each key AMX intrinsic at O0.
// In theory, one tile config can cover several AMX intrinsics, but
diff --git a/llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp b/llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp
index d57871130b0cb29..e71f0eb7363d869 100644
--- a/llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp
+++ b/llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp
@@ -95,7 +95,8 @@ bool X86SpeculativeExecutionSideEffectSuppression::runOnMachineFunction(
// user explicitly passed an SESES flag, or whether the SESES target feature
// was set.
if (!EnableSpeculativeExecutionSideEffectSuppression &&
- !(Subtarget.useLVILoadHardening() && OptLevel == CodeGenOpt::None) &&
+ !(Subtarget.useLVILoadHardening() &&
+ OptLevel == CodeGenOpt::Level::None) &&
!Subtarget.useSpeculativeExecutionSideEffectSuppression())
return false;
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index 14f37e6ac212e5c..c061b2d2cb3d32e 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -443,7 +443,7 @@ void X86PassConfig::addIRPasses() {
TargetPassConfig::addIRPasses();
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOpt::Level::None) {
addPass(createInterleavedAccessPass());
addPass(createX86PartialReductionPass());
}
@@ -473,7 +473,7 @@ bool X86PassConfig::addInstSelector() {
// For ELF, cleanup any local-dynamic TLS accesses.
if (TM->getTargetTriple().isOSBinFormatELF() &&
- getOptLevel() != CodeGenOpt::None)
+ getOptLevel() != CodeGenOpt::Level::None)
addPass(createCleanupLocalDynamicTLSPass());
addPass(createX86GlobalBaseRegPass());
@@ -518,7 +518,7 @@ bool X86PassConfig::addPreISel() {
}
void X86PassConfig::addPreRegAlloc() {
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
addPass(&LiveRangeShrinkID);
addPass(createX86FixupSetCC());
addPass(createX86OptimizeLEAs());
@@ -530,7 +530,7 @@ void X86PassConfig::addPreRegAlloc() {
addPass(createX86FlagsCopyLoweringPass());
addPass(createX86DynAllocaExpander());
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(createX86PreTileConfigPass());
else
addPass(createX86FastPreTileConfigPass());
@@ -548,7 +548,7 @@ void X86PassConfig::addPostRegAlloc() {
// to using the Speculative Execution Side Effect Suppression pass for
// mitigation. This is to prevent slow downs due to
// analyses needed by the LVIHardening pass when compiling at -O0.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::Level::None)
addPass(createX86LoadValueInjectionLoadHardeningPass());
}
@@ -558,7 +558,7 @@ void X86PassConfig::addPreSched2() {
}
void X86PassConfig::addPreEmitPass() {
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
addPass(new X86ExecutionDomainFix());
addPass(createBreakFalseDeps());
}
@@ -567,7 +567,7 @@ void X86PassConfig::addPreEmitPass() {
addPass(createX86IssueVZeroUpperPass());
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::Level::None) {
addPass(createX86FixupBWInsts());
addPass(createX86PadShortFunctions());
addPass(createX86FixupLEAs());
diff --git a/llvm/tools/gold/gold-plugin.cpp b/llvm/tools/gold/gold-plugin.cpp
index d43f27d9216ab07..038032f691ac390 100644
--- a/llvm/tools/gold/gold-plugin.cpp
+++ b/llvm/tools/gold/gold-plugin.cpp
@@ -924,7 +924,7 @@ static std::unique_ptr<LTO> createLTO(IndexWriteCallback OnIndexWrite,
/* UseInputModulePath */ true));
break;
case options::OT_ASM_ONLY:
- Conf.CGFileType = CGFT_AssemblyFile;
+ Conf.CGFileType = CodeGenFileType::AssemblyFile;
break;
}
diff --git a/llvm/tools/llc/llc.cpp b/llvm/tools/llc/llc.cpp
index 8934130f99133cb..81547815d11d095 100644
--- a/llvm/tools/llc/llc.cpp
+++ b/llvm/tools/llc/llc.cpp
@@ -250,7 +250,7 @@ static std::unique_ptr<ToolOutputFile> GetOutputStream(const char *TargetName,
OutputFilename = std::string(IFN);
switch (codegen::getFileType()) {
- case CGFT_AssemblyFile:
+ case CodeGenFileType::AssemblyFile:
if (TargetName[0] == 'c') {
if (TargetName[1] == 0)
OutputFilename += ".cbe.c";
@@ -261,13 +261,13 @@ static std::unique_ptr<ToolOutputFile> GetOutputStream(const char *TargetName,
} else
OutputFilename += ".s";
break;
- case CGFT_ObjectFile:
+ case CodeGenFileType::ObjectFile:
if (OS == Triple::Win32)
OutputFilename += ".obj";
else
OutputFilename += ".o";
break;
- case CGFT_Null:
+ case CodeGenFileType::Null:
OutputFilename = "-";
break;
}
@@ -277,10 +277,10 @@ static std::unique_ptr<ToolOutputFile> GetOutputStream(const char *TargetName,
// Decide if we need "binary" output.
bool Binary = false;
switch (codegen::getFileType()) {
- case CGFT_AssemblyFile:
+ case CodeGenFileType::AssemblyFile:
break;
- case CGFT_ObjectFile:
- case CGFT_Null:
+ case CodeGenFileType::ObjectFile:
+ case CodeGenFileType::Null:
Binary = true;
break;
}
@@ -665,7 +665,8 @@ static int compileModule(char **argv, LLVMContext &Context) {
// flags.
codegen::setFunctionAttributes(CPUStr, FeaturesStr, *M);
- if (mc::getExplicitRelaxAll() && codegen::getFileType() != CGFT_ObjectFile)
+ if (mc::getExplicitRelaxAll() &&
+ codegen::getFileType() != CodeGenFileType::ObjectFile)
WithColor::warning(errs(), argv[0])
<< ": warning: ignoring -mc-relax-all because filetype != obj";
@@ -676,7 +677,7 @@ static int compileModule(char **argv, LLVMContext &Context) {
// so we can memcmp the contents in CompileTwice mode
SmallVector<char, 0> Buffer;
std::unique_ptr<raw_svector_ostream> BOS;
- if ((codegen::getFileType() != CGFT_AssemblyFile &&
+ if ((codegen::getFileType() != CodeGenFileType::AssemblyFile &&
!Out->os().supportsSeeking()) ||
CompileTwice) {
BOS = std::make_unique<raw_svector_ostream>(Buffer);
diff --git a/llvm/tools/llvm-exegesis/lib/Assembler.cpp b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
index 97b461ebd8e98fc..167fb6373377c28 100644
--- a/llvm/tools/llvm-exegesis/lib/Assembler.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
@@ -299,7 +299,8 @@ Error assembleToStream(const ExegesisTarget &ET,
TPC->setInitialized();
// AsmPrinter is responsible for generating the assembly into AsmBuffer.
- if (TM->addAsmPrinter(PM, AsmStream, nullptr, CGFT_ObjectFile, MCContext))
+ if (TM->addAsmPrinter(PM, AsmStream, nullptr, CodeGenFileType::ObjectFile,
+ MCContext))
return make_error<Failure>("Cannot add AsmPrinter passes");
PM.run(*Module); // Run all the passes
diff --git a/llvm/tools/llvm-isel-fuzzer/llvm-isel-fuzzer.cpp b/llvm/tools/llvm-isel-fuzzer/llvm-isel-fuzzer.cpp
index eda165d55b0be92..f46886da7facf4e 100644
--- a/llvm/tools/llvm-isel-fuzzer/llvm-isel-fuzzer.cpp
+++ b/llvm/tools/llvm-isel-fuzzer/llvm-isel-fuzzer.cpp
@@ -99,7 +99,7 @@ extern "C" int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) {
TargetLibraryInfoImpl TLII(TM->getTargetTriple());
PM.add(new TargetLibraryInfoWrapperPass(TLII));
raw_null_ostream OS;
- TM->addPassesToEmitFile(PM, OS, nullptr, CGFT_Null);
+ TM->addPassesToEmitFile(PM, OS, nullptr, CodeGenFileType::Null);
PM.run(*M);
return 0;
diff --git a/llvm/tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp b/llvm/tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp
index d952ea1b06d993c..5e8d8be3ca90c25 100644
--- a/llvm/tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp
+++ b/llvm/tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp
@@ -213,7 +213,7 @@ extern "C" LLVM_ATTRIBUTE_USED int LLVMFuzzerInitialize(int *argc,
TM.reset(TheTarget->createTargetMachine(
TargetTriple.getTriple(), codegen::getCPUStr(), codegen::getFeaturesStr(),
Options, codegen::getExplicitRelocModel(),
- codegen::getExplicitCodeModel(), CodeGenOpt::Default));
+ codegen::getExplicitCodeModel(), CodeGenOpt::Level::Default));
assert(TM && "Could not allocate target machine!");
// Check that pass pipeline is specified and correct
diff --git a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
index e71072602ec7658..81a3bed9bc2c578 100644
--- a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+++ b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
@@ -787,7 +787,7 @@ llvm::parseReducerWorkItem(StringRef ToolName, StringRef Filename,
std::string FeaturesStr = codegen::getFeaturesStr();
TM = std::unique_ptr<TargetMachine>(TheTarget->createTargetMachine(
TheTriple.getTriple(), CPUStr, FeaturesStr, Options, RM,
- codegen::getExplicitCodeModel(), CodeGenOpt::Default));
+ codegen::getExplicitCodeModel(), CodeGenOpt::Level::Default));
assert(TM && "Could not allocate target machine!");
return TM->createDataLayout().getStringRepresentation();
diff --git a/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp b/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp
index 47529f3b1134534..49e0405dff122c3 100644
--- a/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp
+++ b/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp
@@ -42,7 +42,7 @@ class AArch64SelectionDAGTest : public testing::Test {
TargetOptions Options;
TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
T->createTargetMachine("AArch64", "", "+sve", Options, std::nullopt,
- std::nullopt, CodeGenOpt::Aggressive)));
+ std::nullopt, CodeGenOpt::Level::Aggressive)));
if (!TM)
GTEST_SKIP();
@@ -61,7 +61,7 @@ class AArch64SelectionDAGTest : public testing::Test {
MF = std::make_unique<MachineFunction>(*F, *TM, *TM->getSubtargetImpl(*F), 0,
MMI);
- DAG = std::make_unique<SelectionDAG>(*TM, CodeGenOpt::None);
+ DAG = std::make_unique<SelectionDAG>(*TM, CodeGenOpt::Level::None);
if (!DAG)
report_fatal_error("DAG?");
OptimizationRemarkEmitter ORE(F);
diff --git a/llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp b/llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp
index ed2aa552822a0c9..4f4112dd7f90527 100644
--- a/llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp
+++ b/llvm/unittests/CodeGen/AMDGPUMetadataTest.cpp
@@ -70,7 +70,7 @@ class AMDGPUSelectionDAGTest : public testing::Test {
PM.add(new AddMetadataPass(PalMDString));
raw_svector_ostream OutStream(Elf);
if (TM->addPassesToEmitFile(PM, OutStream, nullptr,
- CodeGenFileType::CGFT_ObjectFile))
+ CodeGenFileType::ObjectFile))
report_fatal_error("Target machine cannot emit a file of this type");
PM.run(*M);
diff --git a/llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp b/llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp
index 602ecc71221b6c6..e6ccbd4759aadff 100644
--- a/llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp
@@ -40,7 +40,7 @@ AArch64GISelMITest::createTargetMachine() const {
TargetOptions Options;
return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
T->createTargetMachine("AArch64", "", "", Options, std::nullopt,
- std::nullopt, CodeGenOpt::Aggressive)));
+ std::nullopt, CodeGenOpt::Level::Aggressive)));
}
void AArch64GISelMITest::getTargetTestModuleString(SmallString<512> &S,
@@ -79,7 +79,7 @@ AMDGPUGISelMITest::createTargetMachine() const {
return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
T->createTargetMachine("amdgcn-amd-amdhsa", "gfx900", "", Options,
std::nullopt, std::nullopt,
- CodeGenOpt::Aggressive)));
+ CodeGenOpt::Level::Aggressive)));
}
void AMDGPUGISelMITest::getTargetTestModuleString(
diff --git a/llvm/unittests/CodeGen/InstrRefLDVTest.cpp b/llvm/unittests/CodeGen/InstrRefLDVTest.cpp
index aad99a1099d29b1..7bcaaaf1e8cd188 100644
--- a/llvm/unittests/CodeGen/InstrRefLDVTest.cpp
+++ b/llvm/unittests/CodeGen/InstrRefLDVTest.cpp
@@ -81,7 +81,7 @@ class InstrRefLDVTest : public testing::Test {
TargetOptions Options;
Machine = std::unique_ptr<TargetMachine>(T->createTargetMachine(
Triple::normalize("x86_64--"), "", "", Options, std::nullopt,
- std::nullopt, CodeGenOpt::Aggressive));
+ std::nullopt, CodeGenOpt::Level::Aggressive));
auto Type = FunctionType::get(Type::getVoidTy(Ctx), false);
auto F =
diff --git a/llvm/unittests/CodeGen/MFCommon.inc b/llvm/unittests/CodeGen/MFCommon.inc
index 4fa18accb0d07cf..436c57c69d80456 100644
--- a/llvm/unittests/CodeGen/MFCommon.inc
+++ b/llvm/unittests/CodeGen/MFCommon.inc
@@ -106,7 +106,7 @@ public:
BogusTargetMachine()
: LLVMTargetMachine(Target(), "", Triple(""), "", "",
getTargetOptionsForBogusMachine(), Reloc::Static,
- CodeModel::Small, CodeGenOpt::Default),
+ CodeModel::Small, CodeGenOpt::Level::Default),
ST(*this) {}
~BogusTargetMachine() override {}
diff --git a/llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp b/llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp
index a8e868d8d4041ac..117a8cafe513437 100644
--- a/llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp
+++ b/llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp
@@ -48,7 +48,7 @@ class SelectionDAGAddressAnalysisTest : public testing::Test {
TargetOptions Options;
TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
T->createTargetMachine("AArch64", "", "+sve", Options, std::nullopt,
- std::nullopt, CodeGenOpt::Aggressive)));
+ std::nullopt, CodeGenOpt::Level::Aggressive)));
if (!TM)
GTEST_SKIP();
@@ -73,7 +73,7 @@ class SelectionDAGAddressAnalysisTest : public testing::Test {
MF = std::make_unique<MachineFunction>(*F, *TM, *TM->getSubtargetImpl(*F),
0, MMI);
- DAG = std::make_unique<SelectionDAG>(*TM, CodeGenOpt::None);
+ DAG = std::make_unique<SelectionDAG>(*TM, CodeGenOpt::Level::None);
if (!DAG)
report_fatal_error("DAG?");
OptimizationRemarkEmitter ORE(F);
diff --git a/llvm/unittests/CodeGen/TargetOptionsTest.cpp b/llvm/unittests/CodeGen/TargetOptionsTest.cpp
index e9d8d9a653c2e72..3d109cda7c6de4d 100644
--- a/llvm/unittests/CodeGen/TargetOptionsTest.cpp
+++ b/llvm/unittests/CodeGen/TargetOptionsTest.cpp
@@ -40,7 +40,7 @@ std::unique_ptr<TargetMachine> createTargetMachine(bool EnableIPRA) {
Options.EnableIPRA = EnableIPRA;
return std::unique_ptr<TargetMachine>(
T->createTargetMachine("X86", "", "", Options, std::nullopt, std::nullopt,
- CodeGenOpt::Aggressive));
+ CodeGenOpt::Level::Aggressive));
}
typedef std::function<void(bool)> TargetOptionsTest;
diff --git a/llvm/unittests/ExecutionEngine/MCJIT/MCJITTestBase.h b/llvm/unittests/ExecutionEngine/MCJIT/MCJITTestBase.h
index e0c4b07a71b08f5..cf2907110c71bcb 100644
--- a/llvm/unittests/ExecutionEngine/MCJIT/MCJITTestBase.h
+++ b/llvm/unittests/ExecutionEngine/MCJIT/MCJITTestBase.h
@@ -274,7 +274,7 @@ class TrivialModuleBuilder {
class MCJITTestBase : public MCJITTestAPICommon, public TrivialModuleBuilder {
protected:
MCJITTestBase()
- : TrivialModuleBuilder(HostTriple), OptLevel(CodeGenOpt::None),
+ : TrivialModuleBuilder(HostTriple), OptLevel(CodeGenOpt::Level::None),
CodeModel(CodeModel::Small), MArch(""), MM(new SectionMemoryManager) {
// The architectures below are known to be compatible with MCJIT as they
// are copied from test/ExecutionEngine/MCJIT/lit.local.cfg and should be
@@ -307,13 +307,13 @@ class MCJITTestBase : public MCJITTestAPICommon, public TrivialModuleBuilder {
EngineBuilder EB(std::move(M));
std::string Error;
TheJIT.reset(EB.setEngineKind(EngineKind::JIT)
- .setMCJITMemoryManager(std::move(MM))
- .setErrorStr(&Error)
- .setOptLevel(CodeGenOpt::None)
- .setMArch(MArch)
- .setMCPU(sys::getHostCPUName())
- //.setMAttrs(MAttrs)
- .create());
+ .setMCJITMemoryManager(std::move(MM))
+ .setErrorStr(&Error)
+ .setOptLevel(CodeGenOpt::Level::None)
+ .setMArch(MArch)
+ .setMCPU(sys::getHostCPUName())
+ //.setMAttrs(MAttrs)
+ .create());
// At this point, we cannot modify the module any more.
assert(TheJIT.get() != NULL && "error creating MCJIT with EngineBuilder");
}
diff --git a/llvm/unittests/ExecutionEngine/Orc/JITTargetMachineBuilderTest.cpp b/llvm/unittests/ExecutionEngine/Orc/JITTargetMachineBuilderTest.cpp
index 40993b618eb5aae..7c1650113fee3db 100644
--- a/llvm/unittests/ExecutionEngine/Orc/JITTargetMachineBuilderTest.cpp
+++ b/llvm/unittests/ExecutionEngine/Orc/JITTargetMachineBuilderTest.cpp
@@ -28,7 +28,7 @@ TEST(ExecutionUtilsTest, JITTargetMachineBuilder) {
JTMB.setCPU("");
JTMB.setRelocationModel(std::nullopt);
JTMB.setCodeModel(std::nullopt);
- JTMB.setCodeGenOptLevel(CodeGenOpt::None);
+ JTMB.setCodeGenOptLevel(CodeGenOpt::Level::None);
JTMB.addFeatures(std::vector<std::string>());
SubtargetFeatures &STF = JTMB.getFeatures();
(void)STF;
diff --git a/llvm/unittests/MI/LiveIntervalTest.cpp b/llvm/unittests/MI/LiveIntervalTest.cpp
index e3b07c9a4353b75..1ffb37d9b831499 100644
--- a/llvm/unittests/MI/LiveIntervalTest.cpp
+++ b/llvm/unittests/MI/LiveIntervalTest.cpp
@@ -50,7 +50,7 @@ std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
TargetOptions Options;
return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
T->createTargetMachine("AMDGPU", "gfx900", "", Options, std::nullopt,
- std::nullopt, CodeGenOpt::Aggressive)));
+ std::nullopt, CodeGenOpt::Level::Aggressive)));
}
std::unique_ptr<Module> parseMIR(LLVMContext &Context,
diff --git a/llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp b/llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp
index feb7c1d0085c405..28f1e9927f43fa2 100644
--- a/llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp
@@ -27,7 +27,8 @@ std::unique_ptr<LLVMTargetMachine> createTargetMachine(const std::string &CPU) {
return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
TheTarget->createTargetMachine(TT, CPU, "", TargetOptions(), std::nullopt,
- std::nullopt, CodeGenOpt::Default)));
+ std::nullopt,
+ CodeGenOpt::Level::Default)));
}
std::unique_ptr<AArch64InstrInfo> createInstrInfo(TargetMachine *TM) {
diff --git a/llvm/unittests/Target/AArch64/AddressingModes.cpp b/llvm/unittests/Target/AArch64/AddressingModes.cpp
index 0da8ca94ca2e6f8..3fa560b88ddaa89 100644
--- a/llvm/unittests/Target/AArch64/AddressingModes.cpp
+++ b/llvm/unittests/Target/AArch64/AddressingModes.cpp
@@ -166,7 +166,7 @@ TEST(AddressingModes, AddressingModes) {
std::unique_ptr<TargetMachine> TM(
T->createTargetMachine(TT, "generic", "", TargetOptions(), std::nullopt,
- std::nullopt, CodeGenOpt::Default));
+ std::nullopt, CodeGenOpt::Level::Default));
AArch64Subtarget ST(TM->getTargetTriple(), TM->getTargetCPU(),
TM->getTargetCPU(), TM->getTargetFeatureString(), *TM,
true);
diff --git a/llvm/unittests/Target/AArch64/InstSizes.cpp b/llvm/unittests/Target/AArch64/InstSizes.cpp
index 76bad4d3e99bda1..e507541ca214e0a 100644
--- a/llvm/unittests/Target/AArch64/InstSizes.cpp
+++ b/llvm/unittests/Target/AArch64/InstSizes.cpp
@@ -25,7 +25,8 @@ std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
TheTarget->createTargetMachine(TT, CPU, FS, TargetOptions(), std::nullopt,
- std::nullopt, CodeGenOpt::Default)));
+ std::nullopt,
+ CodeGenOpt::Level::Default)));
}
std::unique_ptr<AArch64InstrInfo> createInstrInfo(TargetMachine *TM) {
diff --git a/llvm/unittests/Target/AArch64/MatrixRegisterAliasing.cpp b/llvm/unittests/Target/AArch64/MatrixRegisterAliasing.cpp
index b4e2fea90432e0e..cb4e94b0d582ffe 100644
--- a/llvm/unittests/Target/AArch64/MatrixRegisterAliasing.cpp
+++ b/llvm/unittests/Target/AArch64/MatrixRegisterAliasing.cpp
@@ -21,7 +21,8 @@ std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
TheTarget->createTargetMachine(TT, CPU, FS, TargetOptions(), std::nullopt,
- std::nullopt, CodeGenOpt::Default)));
+ std::nullopt,
+ CodeGenOpt::Level::Default)));
}
std::unique_ptr<AArch64InstrInfo> createInstrInfo(TargetMachine *TM) {
diff --git a/llvm/unittests/Target/ARM/InstSizes.cpp b/llvm/unittests/Target/ARM/InstSizes.cpp
index cef9dc2f618e748..7be6cb34e4a768d 100644
--- a/llvm/unittests/Target/ARM/InstSizes.cpp
+++ b/llvm/unittests/Target/ARM/InstSizes.cpp
@@ -83,7 +83,7 @@ TEST(InstSizes, PseudoInst) {
TargetOptions Options;
auto TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
T->createTargetMachine(TT, "generic", "", Options, std::nullopt,
- std::nullopt, CodeGenOpt::Default)));
+ std::nullopt, CodeGenOpt::Level::Default)));
ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
std::string(TM->getTargetFeatureString()),
*static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
diff --git a/llvm/unittests/Target/ARM/MachineInstrTest.cpp b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
index 243b027d95a9cdf..d0fdb6bb6811936 100644
--- a/llvm/unittests/Target/ARM/MachineInstrTest.cpp
+++ b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
@@ -85,7 +85,7 @@ TEST(MachineInstructionDoubleWidthResult, IsCorrect) {
TargetOptions Options;
auto TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
T->createTargetMachine(TT, "generic", "", Options, std::nullopt,
- std::nullopt, CodeGenOpt::Default)));
+ std::nullopt, CodeGenOpt::Level::Default)));
ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
std::string(TM->getTargetFeatureString()),
*static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
@@ -241,7 +241,7 @@ TEST(MachineInstructionHorizontalReduction, IsCorrect) {
TargetOptions Options;
auto TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
T->createTargetMachine(TT, "generic", "", Options, std::nullopt,
- std::nullopt, CodeGenOpt::Default)));
+ std::nullopt, CodeGenOpt::Level::Default)));
ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
std::string(TM->getTargetFeatureString()),
*static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
@@ -340,7 +340,7 @@ TEST(MachineInstructionRetainsPreviousHalfElement, IsCorrect) {
TargetOptions Options;
auto TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
T->createTargetMachine(TT, "generic", "", Options, std::nullopt,
- std::nullopt, CodeGenOpt::Default)));
+ std::nullopt, CodeGenOpt::Level::Default)));
ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
std::string(TM->getTargetFeatureString()),
*static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
@@ -1046,7 +1046,7 @@ TEST(MachineInstrValidTailPredication, IsCorrect) {
TargetOptions Options;
auto TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
T->createTargetMachine(TT, "generic", "", Options, std::nullopt,
- std::nullopt, CodeGenOpt::Default)));
+ std::nullopt, CodeGenOpt::Level::Default)));
ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
std::string(TM->getTargetFeatureString()),
*static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
@@ -1187,7 +1187,7 @@ TEST(MachineInstr, HasSideEffects) {
TargetOptions Options;
auto TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
T->createTargetMachine(TT, "generic", "", Options, std::nullopt,
- std::nullopt, CodeGenOpt::Default)));
+ std::nullopt, CodeGenOpt::Level::Default)));
ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
std::string(TM->getTargetFeatureString()),
*static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
@@ -2067,7 +2067,7 @@ TEST(MachineInstr, MVEVecSize) {
TargetOptions Options;
auto TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
T->createTargetMachine(TT, "generic", "", Options, std::nullopt,
- std::nullopt, CodeGenOpt::Default)));
+ std::nullopt, CodeGenOpt::Level::Default)));
ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
std::string(TM->getTargetFeatureString()),
*static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
diff --git a/llvm/unittests/Target/LoongArch/InstSizes.cpp b/llvm/unittests/Target/LoongArch/InstSizes.cpp
index 1a5d4369c48be56..a0274f530312638 100644
--- a/llvm/unittests/Target/LoongArch/InstSizes.cpp
+++ b/llvm/unittests/Target/LoongArch/InstSizes.cpp
@@ -26,7 +26,8 @@ std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
TheTarget->createTargetMachine(TT, CPU, FS, TargetOptions(), std::nullopt,
- std::nullopt, CodeGenOpt::Default)));
+ std::nullopt,
+ CodeGenOpt::Level::Default)));
}
std::unique_ptr<LoongArchInstrInfo> createInstrInfo(TargetMachine *TM) {
diff --git a/llvm/unittests/Target/PowerPC/AIXRelocModelTest.cpp b/llvm/unittests/Target/PowerPC/AIXRelocModelTest.cpp
index 3e2568a7b8763ec..cf7df6607164b89 100644
--- a/llvm/unittests/Target/PowerPC/AIXRelocModelTest.cpp
+++ b/llvm/unittests/Target/PowerPC/AIXRelocModelTest.cpp
@@ -29,7 +29,7 @@ TEST_F(AIXRelocModelTest, DefalutToPIC) {
std::unique_ptr<TargetMachine> Target(TheTarget->createTargetMachine(
/*TT*/ TheTriple.getTriple(), /*CPU*/ "", /*Features*/ "",
/*Options*/ Options, /*RM*/ std::nullopt, /*CM*/ std::nullopt,
- /*OL*/ CodeGenOpt::Default));
+ /*OL*/ CodeGenOpt::Level::Default));
ASSERT_TRUE(Target) << "Could not allocate target machine!";
// The relocation model on AIX should be forced to PIC regardless.
diff --git a/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp b/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp
index eec1cc28f490bde..c3fccfdbdeb1fe6 100644
--- a/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp
+++ b/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp
@@ -36,7 +36,8 @@ std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
TheTarget->createTargetMachine(TT, CPU, FS, TargetOptions(), std::nullopt,
- std::nullopt, CodeGenOpt::Default)));
+ std::nullopt,
+ CodeGenOpt::Level::Default)));
}
std::unique_ptr<Module> parseMIR(LLVMContext &Context,
diff --git a/llvm/unittests/Target/X86/MachineSizeOptsTest.cpp b/llvm/unittests/Target/X86/MachineSizeOptsTest.cpp
index 84286455a269ea6..f0c75b12ed00754 100644
--- a/llvm/unittests/Target/X86/MachineSizeOptsTest.cpp
+++ b/llvm/unittests/Target/X86/MachineSizeOptsTest.cpp
@@ -33,7 +33,8 @@ std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
TheTarget->createTargetMachine(TT, "", "", TargetOptions(), std::nullopt,
- std::nullopt, CodeGenOpt::Default)));
+ std::nullopt,
+ CodeGenOpt::Level::Default)));
}
class MachineSizeOptsTest : public testing::Test {
diff --git a/llvm/unittests/Target/X86/TernlogTest.cpp b/llvm/unittests/Target/X86/TernlogTest.cpp
index df9d1cc9b2980e6..9f6db0b4fa67a5a 100644
--- a/llvm/unittests/Target/X86/TernlogTest.cpp
+++ b/llvm/unittests/Target/X86/TernlogTest.cpp
@@ -29,7 +29,8 @@ static std::unique_ptr<LLVMTargetMachine> initTM() {
const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
TheTarget->createTargetMachine(TT, "", "", TargetOptions(), std::nullopt,
- std::nullopt, CodeGenOpt::Default)));
+ std::nullopt,
+ CodeGenOpt::Level::Default)));
}
struct TernTester {
diff --git a/mlir/lib/Dialect/GPU/Transforms/SerializeToBlob.cpp b/mlir/lib/Dialect/GPU/Transforms/SerializeToBlob.cpp
index 2758689045df210..edea76fb62ed4af 100644
--- a/mlir/lib/Dialect/GPU/Transforms/SerializeToBlob.cpp
+++ b/mlir/lib/Dialect/GPU/Transforms/SerializeToBlob.cpp
@@ -56,7 +56,7 @@ gpu::SerializeToBlobPass::translateToISA(llvm::Module &llvmModule,
llvm::legacy::PassManager codegenPasses;
if (targetMachine.addPassesToEmitFile(codegenPasses, pstream, nullptr,
- llvm::CGFT_AssemblyFile))
+ llvm::CodeGenFileType::AssemblyFile))
return std::nullopt;
codegenPasses.run(llvmModule);
diff --git a/mlir/lib/Target/LLVM/ModuleToObject.cpp b/mlir/lib/Target/LLVM/ModuleToObject.cpp
index b7594f4cd5bf5e6..a7982dbb6ef0e36 100644
--- a/mlir/lib/Target/LLVM/ModuleToObject.cpp
+++ b/mlir/lib/Target/LLVM/ModuleToObject.cpp
@@ -170,7 +170,7 @@ ModuleToObject::translateToISA(llvm::Module &llvmModule,
llvm::legacy::PassManager codegenPasses;
if (targetMachine.addPassesToEmitFile(codegenPasses, pstream, nullptr,
- llvm::CGFT_AssemblyFile))
+ llvm::CodeGenFileType::AssemblyFile))
return std::nullopt;
codegenPasses.run(llvmModule);
diff --git a/openmp/libomptarget/plugins-nextgen/common/PluginInterface/JIT.cpp b/openmp/libomptarget/plugins-nextgen/common/PluginInterface/JIT.cpp
index 657996ff112aaaa..dfcc58e358b0469 100644
--- a/openmp/libomptarget/plugins-nextgen/common/PluginInterface/JIT.cpp
+++ b/openmp/libomptarget/plugins-nextgen/common/PluginInterface/JIT.cpp
@@ -182,7 +182,8 @@ void JITEngine::codegen(TargetMachine *TM, TargetLibraryInfoImpl *TLII,
MachineModuleInfoWrapperPass *MMIWP = new MachineModuleInfoWrapperPass(
reinterpret_cast<LLVMTargetMachine *>(TM));
TM->addPassesToEmitFile(PM, OS, nullptr,
- TT.isNVPTX() ? CGFT_AssemblyFile : CGFT_ObjectFile,
+ TT.isNVPTX() ? CodeGenFileType::AssemblyFile
+ : CodeGenFileType::ObjectFile,
/* DisableVerify */ false, MMIWP);
PM.run(M);
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