[clang-tools-extra] [AArch64] Separate PNR into its own Register Class (PR #65306)
via cfe-commits
cfe-commits at lists.llvm.org
Wed Sep 13 05:20:33 PDT 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
<details>
<summary>Changes</summary>
This patch separates PNR registers into their own register class instead of sharing a register class with PPR registers. This primarily allows us to return more accurate register classes when applying assembly constraints, but also more protection from supplying an incorrect predicate type to an invalid register operand.
--
Patch is 78.79 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/65306.diff
20 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp (+2)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.cpp (+36)
- (modified) llvm/lib/Target/AArch64/AArch64RegisterInfo.td (+106-66)
- (modified) llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td (+12-12)
- (modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (+27-16)
- (modified) llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (+18-3)
- (modified) llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp (+7-2)
- (modified) llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h (-1)
- (modified) llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp (+11)
- (modified) llvm/lib/Target/AArch64/SMEInstrFormats.td (+8-8)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll (+11-12)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll (+3)
- (modified) llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll (+13-13)
- (modified) llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/peephole-insvigpr.mir (+1-2)
- (modified) llvm/test/CodeGen/AArch64/preserve.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/spillfill-sve.mir (+45)
- (modified) llvm/test/MC/AArch64/SVE/cntp-diagnostics.s (+1-1)
<pre>
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index aa7efc65949ae42..f4d3a85f34c88da 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -974,6 +974,8 @@ bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
RegClass = &AArch64::ZPRRegClass;
} else if (AArch64::PPRRegClass.contains(Reg)) {
RegClass = &AArch64::PPRRegClass;
+ } else if (AArch64::PNRRegClass.contains(Reg)) {
+ RegClass = &AArch64::PNRRegClass;
} else {
RegClass = &AArch64::FPR128RegClass;
AltName = AArch64::vreg;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 3a18f37e31185d2..91d5dffaba11c9a 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -3668,6 +3668,32 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
return;
}
+ if (AArch64::PNRRegClass.contains(DestReg) &&
+ AArch64::PPRRegClass.contains(SrcReg)) {
+ assert(Subtarget.hasSVEorSME() && "Unexpected SVE register.");
+ if ((DestReg.id() - AArch64::PN0) == (SrcReg.id() - AArch64::P0))
+ return;
+ DestReg = DestReg - AArch64::PN0 + AArch64::P0;
+ BuildMI(MBB, I, DL, get(AArch64::ORR_PPzPP), DestReg)
+ .addReg(SrcReg)
+ .addReg(SrcReg)
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ return;
+ }
+
+ if (AArch64::PPRRegClass.contains(DestReg) &&
+ AArch64::PNRRegClass.contains(SrcReg)) {
+ assert(Subtarget.hasSVEorSME() && "Unexpected SVE register.");
+ if ((DestReg.id() - AArch64::P0) == (SrcReg.id() - AArch64::PN0))
+ return;
+ SrcReg = (SrcReg - AArch64::PN0) + AArch64::P0;
+ BuildMI(MBB, I, DL, get(AArch64::ORR_PPzPP), DestReg)
+ .addReg(SrcReg)
+ .addReg(SrcReg)
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ return;
+ }
+
// Copy a Z register by ORRing with itself.
if (AArch64::ZPRRegClass.contains(DestReg) &&
AArch64::ZPRRegClass.contains(SrcReg)) {
@@ -3975,6 +4001,11 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
"Unexpected register store without SVE store instructions");
Opc = AArch64::STR_PXI;
StackID = TargetStackID::ScalableVector;
+ } else if (AArch64::PNRRegClass.hasSubClassEq(RC)) {
+ assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
+ "Unexpected register store without SVE2p1 or SME2");
+ Opc = AArch64::STR_PXI;
+ StackID = TargetStackID::ScalableVector;
}
break;
case 4:
@@ -4138,6 +4169,11 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
"Unexpected register load without SVE load instructions");
Opc = AArch64::LDR_PXI;
StackID = TargetStackID::ScalableVector;
+ } else if (AArch64::PNRRegClass.hasSubClassEq(RC)) {
+ assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
+ "Unexpected register load without SVE2p1 or SME2");
+ Opc = AArch64::LDR_PXI;
+ StackID = TargetStackID::ScalableVector;
}
break;
case 4:
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index 18fc8c77a0e44d9..3f74c74ad1d6d8d 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -55,6 +55,8 @@ let Namespace = "AArch64" in {
def zasubd1 : SubRegIndex<256>; // (16 x 16)/8 bytes = 256 bits
def zasubq0 : SubRegIndex<128>; // (16 x 16)/16 bytes = 128 bits
def zasubq1 : SubRegIndex<128>; // (16 x 16)/16 bytes = 128 bits
+
+ def psub : SubRegIndex<16>;
}
let Namespace = "AArch64" in {
@@ -767,23 +769,43 @@ def GPR64x8 : RegisterOperand<GPR64x8Class, "printGPR64x8"> {
//===----- END: v8.7a accelerator extension register operands -------------===//
+// SVE predicate-as-counter registers
+ def PN0 : AArch64Reg<0, "pn0">, DwarfRegNum<[48]>;
+ def PN1 : AArch64Reg<1, "pn1">, DwarfRegNum<[49]>;
+ def PN2 : AArch64Reg<2, "pn2">, DwarfRegNum<[50]>;
+ def PN3 : AArch64Reg<3, "pn3">, DwarfRegNum<[51]>;
+ def PN4 : AArch64Reg<4, "pn4">, DwarfRegNum<[52]>;
+ def PN5 : AArch64Reg<5, "pn5">, DwarfRegNum<[53]>;
+ def PN6 : AArch64Reg<6, "pn6">, DwarfRegNum<[54]>;
+ def PN7 : AArch64Reg<7, "pn7">, DwarfRegNum<[55]>;
+ def PN8 : AArch64Reg<8, "pn8">, DwarfRegNum<[56]>;
+ def PN9 : AArch64Reg<9, "pn9">, DwarfRegNum<[57]>;
+ def PN10 : AArch64Reg<10, "pn10">, DwarfRegNum<[58]>;
+ def PN11 : AArch64Reg<11, "pn11">, DwarfRegNum<[59]>;
+ def PN12 : AArch64Reg<12, "pn12">, DwarfRegNum<[60]>;
+ def PN13 : AArch64Reg<13, "pn13">, DwarfRegNum<[61]>;
+ def PN14 : AArch64Reg<14, "pn14">, DwarfRegNum<[62]>;
+ def PN15 : AArch64Reg<15, "pn15">, DwarfRegNum<[63]>;
+
// SVE predicate registers
-def P0 : AArch64Reg<0, "p0">, DwarfRegNum<[48]>;
-def P1 : AArch64Reg<1, "p1">, DwarfRegNum<[49]>;
-def P2 : AArch64Reg<2, "p2">, DwarfRegNum<[50]>;
-def P3 : AArch64Reg<3, "p3">, DwarfRegNum<[51]>;
-def P4 : AArch64Reg<4, "p4">, DwarfRegNum<[52]>;
-def P5 : AArch64Reg<5, "p5">, DwarfRegNum<[53]>;
-def P6 : AArch64Reg<6, "p6">, DwarfRegNum<[54]>;
-def P7 : AArch64Reg<7, "p7">, DwarfRegNum<[55]>;
-def P8 : AArch64Reg<8, "p8">, DwarfRegNum<[56]>;
-def P9 : AArch64Reg<9, "p9">, DwarfRegNum<[57]>;
-def P10 : AArch64Reg<10, "p10">, DwarfRegNum<[58]>;
-def P11 : AArch64Reg<11, "p11">, DwarfRegNum<[59]>;
-def P12 : AArch64Reg<12, "p12">, DwarfRegNum<[60]>;
-def P13 : AArch64Reg<13, "p13">, DwarfRegNum<[61]>;
-def P14 : AArch64Reg<14, "p14">, DwarfRegNum<[62]>;
-def P15 : AArch64Reg<15, "p15">, DwarfRegNum<[63]>;
+let SubRegIndices = [psub] in {
+ def P0 : AArch64Reg<0, "p0", [PN0]>, DwarfRegAlias<PN0>;
+ def P1 : AArch64Reg<1, "p1", [PN1]>, DwarfRegAlias<PN1>;
+ def P2 : AArch64Reg<2, "p2", [PN2]>, DwarfRegAlias<PN2>;
+ def P3 : AArch64Reg<3, "p3", [PN3]>, DwarfRegAlias<PN3>;
+ def P4 : AArch64Reg<4, "p4", [PN4]>, DwarfRegAlias<PN4>;
+ def P5 : AArch64Reg<5, "p5", [PN5]>, DwarfRegAlias<PN5>;
+ def P6 : AArch64Reg<6, "p6", [PN6]>, DwarfRegAlias<PN6>;
+ def P7 : AArch64Reg<7, "p7", [PN7]>, DwarfRegAlias<PN7>;
+ def P8 : AArch64Reg<8, "p8", [PN8]>, DwarfRegAlias<PN8>;
+ def P9 : AArch64Reg<9, "p9", [PN9]>, DwarfRegAlias<PN9>;
+ def P10 : AArch64Reg<10, "p10", [PN10]>, DwarfRegAlias<PN10>;
+ def P11 : AArch64Reg<11, "p11", [PN11]>, DwarfRegAlias<PN11>;
+ def P12 : AArch64Reg<12, "p12", [PN12]>, DwarfRegAlias<PN12>;
+ def P13 : AArch64Reg<13, "p13", [PN13]>, DwarfRegAlias<PN13>;
+ def P14 : AArch64Reg<14, "p14", [PN14]>, DwarfRegAlias<PN14>;
+ def P15 : AArch64Reg<15, "p15", [PN15]>, DwarfRegAlias<PN15>;
+}
// The part of SVE registers that don't overlap Neon registers.
// These are only used as part of clobber lists.
@@ -881,8 +903,6 @@ class SVERegOp <string Suffix, AsmOperandClass C,
let ParserMatchClass = C;
}
-class PPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,
- RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}
class ZPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,
RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}
@@ -891,7 +911,7 @@ class ZPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,
// SVE predicate register classes.
class PPRClass<int firstreg, int lastreg> : RegisterClass<
"AArch64",
- [ nxv16i1, nxv8i1, nxv4i1, nxv2i1, nxv1i1, aarch64svcount ], 16,
+ [ nxv16i1, nxv8i1, nxv4i1, nxv2i1, nxv1i1 ], 16,
(sequence "P%u", firstreg, lastreg)> {
let Size = 16;
}
@@ -909,69 +929,89 @@ class PPRAsmOperand <string name, string RegClass, int Width>: AsmOperandClass {
let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateVector>";
}
-def PPRAsmOpAny : PPRAsmOperand<"PredicateAny", "PPR", 0>;
-def PPRAsmOp8 : PPRAsmOperand<"PredicateB", "PPR", 8>;
-def PPRAsmOp16 : PPRAsmOperand<"PredicateH", "PPR", 16>;
-def PPRAsmOp32 : PPRAsmOperand<"PredicateS", "PPR", 32>;
-def PPRAsmOp64 : PPRAsmOperand<"PredicateD", "PPR", 64>;
-
-def PPRAny : PPRRegOp<"", PPRAsmOpAny, ElementSizeNone, PPR>;
-def PPR8 : PPRRegOp<"b", PPRAsmOp8, ElementSizeB, PPR>;
-def PPR16 : PPRRegOp<"h", PPRAsmOp16, ElementSizeH, PPR>;
-def PPR32 : PPRRegOp<"s", PPRAsmOp32, ElementSizeS, PPR>;
-def PPR64 : PPRRegOp<"d", PPRAsmOp64, ElementSizeD, PPR>;
-
+def PPRAsmOpAny : PPRAsmOperand<"PredicateAny", "PPR", 0>;
+def PPRAsmOp8 : PPRAsmOperand<"PredicateB", "PPR", 8>;
+def PPRAsmOp16 : PPRAsmOperand<"PredicateH", "PPR", 16>;
+def PPRAsmOp32 : PPRAsmOperand<"PredicateS", "PPR", 32>;
+def PPRAsmOp64 : PPRAsmOperand<"PredicateD", "PPR", 64>;
def PPRAsmOp3bAny : PPRAsmOperand<"Predicate3bAny", "PPR_3b", 0>;
+class PPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,
+ RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}
+
+def PPRAny : PPRRegOp<"", PPRAsmOpAny, ElementSizeNone, PPR>;
+def PPR8 : PPRRegOp<"b", PPRAsmOp8, ElementSizeB, PPR>;
+def PPR16 : PPRRegOp<"h", PPRAsmOp16, ElementSizeH, PPR>;
+def PPR32 : PPRRegOp<"s", PPRAsmOp32, ElementSizeS, PPR>;
+def PPR64 : PPRRegOp<"d", PPRAsmOp64, ElementSizeD, PPR>;
def PPR3bAny : PPRRegOp<"", PPRAsmOp3bAny, ElementSizeNone, PPR_3b>;
+class PNRClass<int firstreg, int lastreg> : RegisterClass<
+ "AArch64",
+ [ aarch64svcount ], 16,
+ (sequence "PN%u", firstreg, lastreg)> {
+ let Size = 16;
+}
+
+def PNR : PNRClass<0, 15>;
+def PNR_p8to15 : PNRClass<8, 15>;
// SVE predicate-as-counter operand
-class PNRAsmOperand<string name, string RegClass, int Width>
- : PPRAsmOperand<name, RegClass, Width> {
+class PNRAsmOperand<string name, string RegClass, int Width>: AsmOperandClass {
+ let Name = "SVE" # name # "Reg";
let PredicateMethod = "isSVEPredicateAsCounterRegOfWidth<"
# Width # ", " # "AArch64::"
# RegClass # "RegClassID>";
let DiagnosticType = "InvalidSVE" # name # "Reg";
+ let RenderMethod = "addRegOperands";
let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>";
}
-class PNRRegOp<string Suffix, AsmOperandClass C, int EltSize, RegisterClass RC>
- : PPRRegOp<Suffix, C, ElementSizeNone, RC> {
- let PrintMethod = "printPredicateAsCounter<" # EltSize # ">";
+let RenderMethod = "addPNRasPPRRegOperands" in {
+ def PNRasPPROpAny : PNRAsmOperand<"PNRasPPRPredicateAny", "PNR", 0>;
+ def PNRasPPROp8 : PNRAsmOperand<"PNRasPPRPredicateB", "PNR", 8>;
}
-def PNRAsmOpAny: PNRAsmOperand<"PNPredicateAny", "PPR", 0>;
-def PNRAsmOp8 : PNRAsmOperand<"PNPredicateB", "PPR", 8>;
-def PNRAsmOp16 : PNRAsmOperand<"PNPredicateH", "PPR", 16>;
-def PNRAsmOp32 : PNRAsmOperand<"PNPredicateS", "PPR", 32>;
-def PNRAsmOp64 : PNRAsmOperand<"PNPredicateD", "PPR", 64>;
-
-def PNRAny : PNRRegOp<"", PNRAsmOpAny, 0, PPR>;
-def PNR8 : PNRRegOp<"b", PNRAsmOp8, 8, PPR>;
-def PNR16 : PNRRegOp<"h", PNRAsmOp16, 16, PPR>;
-def PNR32 : PNRRegOp<"s", PNRAsmOp32, 32, PPR>;
-def PNR64 : PNRRegOp<"d", PNRAsmOp64, 64, PPR>;
-
-class PNRP8to15RegOp<string Suffix, AsmOperandClass C, int EltSize, RegisterClass RC>
- : PPRRegOp<Suffix, C, ElementSizeNone, RC> {
- let PrintMethod = "printPredicateAsCounter<" # EltSize # ">";
- let EncoderMethod = "EncodePPR_p8to15";
- let DecoderMethod = "DecodePPR_p8to15RegisterClass";
-}
-
-def PNRAsmAny_p8to15 : PNRAsmOperand<"PNPredicateAny_p8to15", "PPR_p8to15", 0>;
-def PNRAsmOp8_p8to15 : PNRAsmOperand<"PNPredicateB_p8to15", "PPR_p8to15", 8>;
-def PNRAsmOp16_p8to15 : PNRAsmOperand<"PNPredicateH_p8to15", "PPR_p8to15", 16>;
-def PNRAsmOp32_p8to15 : PNRAsmOperand<"PNPredicateS_p8to15", "PPR_p8to15", 32>;
-def PNRAsmOp64_p8to15 : PNRAsmOperand<"PNPredicateD_p8to15", "PPR_p8to15", 64>;
-
-def PNRAny_p8to15 : PNRP8to15RegOp<"", PNRAsmAny_p8to15, 0, PPR_p8to15>;
-def PNR8_p8to15 : PNRP8to15RegOp<"b", PNRAsmOp8_p8to15, 8, PPR_p8to15>;
-def PNR16_p8to15 : PNRP8to15RegOp<"h", PNRAsmOp16_p8to15, 16, PPR_p8to15>;
-def PNR32_p8to15 : PNRP8to15RegOp<"s", PNRAsmOp32_p8to15, 32, PPR_p8to15>;
-def PNR64_p8to15 : PNRP8to15RegOp<"d", PNRAsmOp64_p8to15, 64, PPR_p8to15>;
+class PNRasPPRRegOp<string Suffix, AsmOperandClass C, ElementSizeEnum Size,
+ RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}
+def PNRasPPRAny : PNRasPPRRegOp<"", PNRasPPROpAny, ElementSizeNone, PPR>;
+def PNRasPPR8 : PNRasPPRRegOp<"b", PNRasPPROp8, ElementSizeB, PPR>;
+
+def PNRAsmOpAny: PNRAsmOperand<"PNPredicateAny", "PNR", 0>;
+def PNRAsmOp8 : PNRAsmOperand<"PNPredicateB", "PNR", 8>;
+def PNRAsmOp16 : PNRAsmOperand<"PNPredicateH", "PNR", 16>;
+def PNRAsmOp32 : PNRAsmOperand<"PNPredicateS", "PNR", 32>;
+def PNRAsmOp64 : PNRAsmOperand<"PNPredicateD", "PNR", 64>;
+
+class PNRRegOp<string Suffix, AsmOperandClass C, int Size, RegisterClass RC>
+ : SVERegOp<Suffix, C, ElementSizeNone, RC> {
+ let PrintMethod = "printPredicateAsCounter<" # Size # ">";
+}
+def PNRAny : PNRRegOp<"", PNRAsmOpAny, 0, PNR>;
+def PNR8 : PNRRegOp<"b", PNRAsmOp8, 8, PNR>;
+def PNR16 : PNRRegOp<"h", PNRAsmOp16, 16, PNR>;
+def PNR32 : PNRRegOp<"s", PNRAsmOp32, 32, PNR>;
+def PNR64 : PNRRegOp<"d", PNRAsmOp64, 64, PNR>;
+
+def PNRAsmAny_p8to15 : PNRAsmOperand<"PNPredicateAny_p8to15", "PNR_p8to15", 0>;
+def PNRAsmOp8_p8to15 : PNRAsmOperand<"PNPredicateB_p8to15", "PNR_p8to15", 8>;
+def PNRAsmOp16_p8to15 : PNRAsmOperand<"PNPredicateH_p8to15", "PNR_p8to15", 16>;
+def PNRAsmOp32_p8to15 : PNRAsmOperand<"PNPredicateS_p8to15", "PNR_p8to15", 32>;
+def PNRAsmOp64_p8to15 : PNRAsmOperand<"PNPredicateD_p8to15", "PNR_p8to15", 64>;
+
+class PNRP8to15RegOp<string Suffix, AsmOperandClass C, int Width, RegisterClass RC>
+ : SVERegOp<Suffix, C, ElementSizeNone, RC> {
+ let PrintMethod = "printPredicateAsCounter<" # Width # ">";
+ let EncoderMethod = "EncodePNR_p8to15";
+ let DecoderMethod = "DecodePNR_p8to15RegisterClass";
+}
+
+def PNRAny_p8to15 : PNRP8to15RegOp<"", PNRAsmAny_p8to15, 0, PNR_p8to15>;
+def PNR8_p8to15 : PNRP8to15RegOp<"b", PNRAsmOp8_p8to15, 8, PNR_p8to15>;
+def PNR16_p8to15 : PNRP8to15RegOp<"h", PNRAsmOp16_p8to15, 16, PNR_p8to15>;
+def PNR32_p8to15 : PNRP8to15RegOp<"s", PNRAsmOp32_p8to15, 32, PNR_p8to15>;
+def PNR64_p8to15 : PNRP8to15RegOp<"d", PNRAsmOp64_p8to15, 64, PNR_p8to15>;
let Namespace = "AArch64" in {
def psub0 : SubRegIndex<16, -1>;
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 9c2b270faef125f..a7a64c6b20d84d3 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -2544,8 +2544,8 @@ let Predicates = [HasSVEorSME] in {
def : Pat<(nxv4f32 (bitconvert (nxv8bf16 ZPR:$src))), (nxv4f32 ZPR:$src)>;
def : Pat<(nxv2f64 (bitconvert (nxv8bf16 ZPR:$src))), (nxv2f64 ZPR:$src)>;
- def : Pat<(nxv16i1 (bitconvert (aarch64svcount PPR:$src))), (nxv16i1 PPR:$src)>;
- def : Pat<(aarch64svcount (bitconvert (nxv16i1 PPR:$src))), (aarch64svcount PPR:$src)>;
+ def : Pat<(nxv16i1 (bitconvert (aarch64svcount PNR:$src))), (nxv16i1 PPR:$src)>;
+ def : Pat&l...
<truncated>
</pre>
</details>
https://github.com/llvm/llvm-project/pull/65306
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