[clang] Implement ACLE rintn and rintnf intrinsics (PR #66112)

[M Iyengar via cfe-commits]

https://github.com/Blue-Dot created https://github.com/llvm/llvm-project/pull/66112:

This patch adds support for two missing ACLE intrinsics for floating point round with ties to even:

- rintn
- rintnf

These are specified in ACLE section 8.6: [https://arm-software.github.io/acle/main/acle.html#floating-point-data-processing-intrinsics]

Change-Id: I951971ad5a3fd3822efdf8cbae22918c31eef28a

>From c36fd81936845d1bc2f69dbb86372c554e1e9dba Mon Sep 17 00:00:00 2001
From: Max Iyengar <Max.Iyengar at arm.com>
Date: Tue, 12 Sep 2023 15:20:57 +0100
Subject: [PATCH] Implement ACLE rintn and rintnf intrinsics

Change-Id: I951971ad5a3fd3822efdf8cbae22918c31eef28a
---
 clang/include/clang/Basic/BuiltinsAArch64.def |  4 ++++
 clang/lib/CodeGen/CGBuiltin.cpp               |  7 +++++++
 clang/lib/Headers/arm_acle.h                  | 15 +++++++++++++++
 clang/test/CodeGen/arm_acle.c                 | 16 ++++++++++++++++
 4 files changed, 42 insertions(+)

diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def b/clang/include/clang/Basic/BuiltinsAArch64.def
index eaae6c9ad846868..017138bd34f8bd5 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.def
+++ b/clang/include/clang/Basic/BuiltinsAArch64.def
@@ -110,6 +110,10 @@ BUILTIN(__builtin_arm_tcommit, "v", "n")
 BUILTIN(__builtin_arm_tcancel, "vWUIi", "n")
 BUILTIN(__builtin_arm_ttest, "WUi", "nc")
 
+// Floating point round to integral intrinsics
+BUILTIN(__builtin_arm_rintn, "dd", "g")
+BUILTIN(__builtin_arm_rintnf, "ff", "g")
+
 // Armv8.5-A FP rounding intrinsics
 TARGET_BUILTIN(__builtin_arm_rint32zf, "ff", "", "v8.5a")
 TARGET_BUILTIN(__builtin_arm_rint32z, "dd", "", "v8.5a")
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 1ee0c469af9ee8b..b594923e11e145a 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -10224,6 +10224,13 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
                               "cls");
   }
 
+  if (BuiltinID == clang::AArch64::BI__builtin_arm_rintn ||
+      BuiltinID == clang::AArch64::BI__builtin_arm_rintnf) {
+    llvm::Value *Arg = EmitScalarExpr(E->getArg(0));
+    return Builder.CreateCall(
+        CGM.getIntrinsic(Intrinsic::roundeven, Arg->getType()), Arg, "rintn");
+  }
+
   if (BuiltinID == clang::AArch64::BI__builtin_arm_rint32zf ||
       BuiltinID == clang::AArch64::BI__builtin_arm_rint32z) {
     llvm::Value *Arg = EmitScalarExpr(E->getArg(0));
diff --git a/clang/lib/Headers/arm_acle.h b/clang/lib/Headers/arm_acle.h
index c208512bab59829..cb1fb596a41fc93 100644
--- a/clang/lib/Headers/arm_acle.h
+++ b/clang/lib/Headers/arm_acle.h
@@ -592,6 +592,21 @@ __smusdx(int16x2_t __a, int16x2_t __b) {
 }
 #endif
 
+/* 8.6 Floating-point data-processing intrinsics */
+#if (defined(__ARM_FEATURE_DIRECTED_ROUNDING)    &&                         \
+  (__ARM_FEATURE_DIRECTED_ROUNDING))             &&                         \
+  (defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE)
+static __inline__ double __attribute__((__always_inline__, __nodebug__))
+__rintn(double __a) {
+  return __builtin_arm_rintn(__a);
+}
+
+static __inline__ float __attribute__((__always_inline__, __nodebug__))
+__rintnf(float __a) {
+  return __builtin_arm_rintnf(__a);
+}
+#endif
+
 /* 9.7 CRC32 intrinsics */
 #if (defined(__ARM_FEATURE_CRC32) && __ARM_FEATURE_CRC32) ||                   \
     (defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE)
diff --git a/clang/test/CodeGen/arm_acle.c b/clang/test/CodeGen/arm_acle.c
index b1105a1d5aabb64..00afaf15fded392 100644
--- a/clang/test/CodeGen/arm_acle.c
+++ b/clang/test/CodeGen/arm_acle.c
@@ -1690,6 +1690,22 @@ int32_t test_jcvt(double v) {
 }
 #endif
 
+#if defined(__ARM_FEATURE_DIRECTED_ROUNDING) && defined(__ARM_64BIT_STATE)
+
+// AArch64-LABEL: @test_rintn(
+// AArch64-NEXT:  entry:
+// AArch64-NEXT:    call double @llvm.roundeven.f64(double [[TMP0:%.*]])
+double test_rintn(double a) {
+  return __rintn(a);
+}
+
+// AArch64-LABEL: @test_rintnf(
+// AArch64-NEXT: entry:
+// AArch64-NEXT:      call float @llvm.roundeven.f32(float [[TMP0:%.*]])
+float test_rintnf(float b) {
+  return __rintnf(b);
+}
+#endif
 
 #if defined(__ARM_64BIT_STATE) && defined(__ARM_FEATURE_RNG)