[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


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Comment at: clang/lib/CodeGen/Targets/RISCV.cpp:479
+  // 2×XLEN-bit alignment and size at most 2×XLEN bits like `long long`,
+  // `unsigned long long` and `double` to have 4-bytes alignment. This
+  // behavior may be changed when RV32E/ILP32E is ratified.
----------------
4-bytes -> 4-byte


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Comment at: clang/test/Preprocessor/riscv-target-features.c:6
 
+// CHECK-NOT: __riscv_32e
 // CHECK-NOT: __riscv_div {{.*$}}
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__riscv_64e too


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Comment at: llvm/lib/Support/RISCVISAInfo.cpp:937
   // TODO: The 'q' extension requires rv64.
-  // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
 
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This needs to be rebased. These FIXMEs were removed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70401/new/

https://reviews.llvm.org/D70401