[PATCH] D159250: [X86][RFC] Add new option `-m[no-]evex512` to disable ZMM and 64-bit mask instructions for AVX512 features

[James Y Knight via Phabricator via cfe-commits]

jyknight added a comment.

In D159250#4633530 <https://reviews.llvm.org/D159250#4633530>, @pengfei wrote:

> In D159250#4631786 <https://reviews.llvm.org/D159250#4631786>, @RKSimon wrote:
>
>> Would it be possible to add function multiversioning tests to ensure the evex512 attribute would work with it?
>
> Function multiversioning is orthogonal to evex512 feature.
>
> When user uses `-mno-evex512` in command line, all the code generation, including function multiversioning are limited to 256-bit vector and 32-bit mask.
>
> User is not suggested to use `avx512xxx,evex512` in function attributes for function multiversioning, because EVEX512 is a software concept and the dispatcher cannot distinguish between `avx512xxx` and `avx512xxx,evex512`.

If the dispatcher is updated to take into account AVX10.1 CPUID, it could distinguish the different hardware support.

That is:

- to check for AVX512xxx with evex512 //enabled//, the dispatcher need only check for the AVX512xxx CPUID bit, since according to the doc, a CPU which implements AVX10.1 with 512-bit register size will also set the corresponding AVX512 CPUID bits. No change there.
- to check for AVX512xxx with evex512 //disabled//, the dispatcher function should check that either CPUID reports the AVX512xxx bit OR that the CPUID reports AVX10.1 with support for at least 256-bit register size. (But only for the 'AVX512xxx' features which are actually included in AVX10.1, of course).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159250/new/

https://reviews.llvm.org/D159250