[clang] 825cec2 - [clang-format] Add Verilog suffixes to the scripts

[via cfe-commits]

Author: sstwcw
Date: 2023-08-24T03:06:45Z
New Revision: 825cec2c0b1ecec49995126674a8e58cd813476c

URL: https://github.com/llvm/llvm-project/commit/825cec2c0b1ecec49995126674a8e58cd813476c
DIFF: https://github.com/llvm/llvm-project/commit/825cec2c0b1ecec49995126674a8e58cd813476c.diff

LOG: [clang-format] Add Verilog suffixes to the scripts

I decided not to wait for D149088 because it was taking a long time.

The capture group in the regexp was changed to non-capturing.  It
doesn't need to be captured.

Reviewed By: HazardyKnusperkeks, owenpan

Differential Revision: https://reviews.llvm.org/D154467

Added: 
    

Modified: 
    clang/tools/clang-format/clang-format-diff.py
    clang/tools/clang-format/git-clang-format

Removed: 
    


################################################################################
diff  --git a/clang/tools/clang-format/clang-format-
diff .py b/clang/tools/clang-format/clang-format-
diff .py
index 6e707fc0fb6471a..324ef5b7f6b35f6 100755
--- a/clang/tools/clang-format/clang-format-
diff .py
+++ b/clang/tools/clang-format/clang-format-
diff .py
@@ -61,8 +61,8 @@ def main():
     parser.add_argument(
         "-iregex",
         metavar="PATTERN",
-        default=r".*\.(cpp|cc|c\+\+|cxx|cppm|ccm|cxxm|c\+\+m|c|cl|h|hh|hpp|hxx"
-        r"|m|mm|inc|js|ts|proto|protodevel|java|cs|json)",
+        default=r".*\.(?:cpp|cc|c\+\+|cxx|cppm|ccm|cxxm|c\+\+m|c|cl|h|hh|hpp"
+        r"|hxx|m|mm|inc|js|ts|proto|protodevel|java|cs|json|s?vh?)",
         help="custom pattern selecting file paths to reformat "
         "(case insensitive, overridden by -regex)",
     )

diff  --git a/clang/tools/clang-format/git-clang-format b/clang/tools/clang-format/git-clang-format
index 695545d9e325522..c0b99b82203234c 100755
--- a/clang/tools/clang-format/git-clang-format
+++ b/clang/tools/clang-format/git-clang-format
@@ -98,6 +98,7 @@ def main():
       'ts',  # TypeScript
       'cs',  # C Sharp
       'json',  # Json
+      'sv', 'svh', 'v', 'vh', # Verilog
       ])
 
   p = argparse.ArgumentParser(