[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

[Jim Lin via Phabricator via cfe-commits]

Jim added inline comments.


================
Comment at: clang/test/CodeGen/riscv-rvv-vla-arith-ops.c:3
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64d \
+// RUN: -target-feature +f -target-feature +d -disable-O0-optnone \
+// RUN: -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - %s | \
----------------
zve64d has implied f and d.


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Comment at: clang/test/CodeGen/riscv-rvv-vla-arith-ops.c:90
+//
+vfloat32m1_t add_f32(vfloat32m1_t a, vfloat32m1_t b) {
+  return a + b;
----------------
Do we support operation for vfloat16 here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158259/new/

https://reviews.llvm.org/D158259