[PATCH] D158008: [AArch64] Add patterns for FMADD, FMSUB

[Vladislav Dzhidzhoev via Phabricator via cfe-commits]

dzhidzhoev added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:5381-5393
+  let Predicates = [HasFullFP16] in {
+  def : Pat<(f16 (node (f16 FPR16:$Rn),
+                       (f16 (vector_extract (v8f16 V128:$Rm), (i64 0))),
+                       (f16 FPR16:$Ra))),
+            (!cast<Instruction>(NAME # Hrrr)
+              FPR16:$Rn, (EXTRACT_SUBREG V128:$Rm, hsub), FPR16:$Ra)>;
+
----------------
The result type of (EXTRACT_SUBREG ...) here seems to be deduced to i16, which causes an assertion after applying this rule.
Explicit specification of the result type fixes crashes of tests:

```
FPR16:$Rn, (f16 (EXTRACT_SUBREG V128:$Rm, hsub)), FPR16:$Ra)>;
```

```
(f16 (EXTRACT_SUBREG V128:$Rn, hsub)), FPR16:$Rm, FPR16:$Ra)>
```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158008/new/

https://reviews.llvm.org/D158008