[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.
Craig Topper via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Wed Aug 16 16:46:08 PDT 2023
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:37
+ let Inst{12} = 0;
+ let Inst{11-7} = rs1;
+ let Inst{6-2} = 0b00000;
----------------
Do we need the rs1 variable or can we use rs1val here? We usually have the rs1 field because the encoder maps ins/outs operand names to the field name. In this case we have an explicit immediate passed as rs1val. Is the encoding value coming from the operand or from the immediate? I can't tell with the name conflict.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D152793/new/
https://reviews.llvm.org/D152793
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