[clang] 36ac6ac - [RISCV] Merge rv32 and rv64 Zvb* intrinsic tests. NFC
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Wed Aug 2 00:14:33 PDT 2023
Author: Craig Topper
Date: 2023-08-02T00:08:01-07:00
New Revision: 36ac6ac1dbd0ffd5a4a5de0d6892141f969c130d
URL: https://github.com/llvm/llvm-project/commit/36ac6ac1dbd0ffd5a4a5de0d6892141f969c130d
DIFF: https://github.com/llvm/llvm-project/commit/36ac6ac1dbd0ffd5a4a5de0d6892141f969c130d.diff
LOG: [RISCV] Merge rv32 and rv64 Zvb* intrinsic tests. NFC
There was some duplication between these tests and
we can merge them by checking __riscv_xlen for the parts
that aren't duplicated.
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D156851
Added:
clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c
clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c
clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c
clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c
clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c
Modified:
Removed:
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
################################################################################
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
deleted file mode 100644
index ffd869ce6d9b0a..00000000000000
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple riscv32 -target-feature +zbb -emit-llvm %s -o - \
-// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
-// RUN: | FileCheck %s -check-prefix=RV32ZBB
-
-// RV32ZBB-LABEL: @orc_b_32(
-// RV32ZBB-NEXT: entry:
-// RV32ZBB-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[A:%.*]])
-// RV32ZBB-NEXT: ret i32 [[TMP0]]
-//
-unsigned int orc_b_32(unsigned int a) {
- return __builtin_riscv_orc_b_32(a);
-}
-
-// RV32ZBB-LABEL: @clz_32(
-// RV32ZBB-NEXT: entry:
-// RV32ZBB-NEXT: [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[A:%.*]], i1 false)
-// RV32ZBB-NEXT: ret i32 [[TMP0]]
-//
-unsigned int clz_32(unsigned int a) {
- return __builtin_riscv_clz_32(a);
-}
-
-// RV32ZBB-LABEL: @ctz_32(
-// RV32ZBB-NEXT: entry:
-// RV32ZBB-NEXT: [[TMP0:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 false)
-// RV32ZBB-NEXT: ret i32 [[TMP0]]
-//
-unsigned int ctz_32(unsigned int a) {
- return __builtin_riscv_ctz_32(a);
-}
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c
deleted file mode 100644
index 12d4e3a179e7f7..00000000000000
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c
+++ /dev/null
@@ -1,50 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple riscv32 -target-feature +zbc -emit-llvm %s -o - \
-// RUN: | FileCheck %s -check-prefix=RV32ZBC
-
-#include <stdint.h>
-
-// RV32ZBC-LABEL: @clmul_32(
-// RV32ZBC-NEXT: entry:
-// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV32ZBC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
-// RV32ZBC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV32ZBC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
-// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
-// RV32ZBC-NEXT: ret i32 [[TMP2]]
-//
-uint32_t clmul_32(uint32_t a, uint32_t b) {
- return __builtin_riscv_clmul_32(a, b);
-}
-
-// RV32ZBC-LABEL: @clmulh_32(
-// RV32ZBC-NEXT: entry:
-// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV32ZBC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
-// RV32ZBC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV32ZBC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
-// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[TMP0]], i32 [[TMP1]])
-// RV32ZBC-NEXT: ret i32 [[TMP2]]
-//
-uint32_t clmulh_32(uint32_t a, uint32_t b) {
- return __builtin_riscv_clmulh_32(a, b);
-}
-
-// RV32ZBC-LABEL: @clmulr_32(
-// RV32ZBC-NEXT: entry:
-// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV32ZBC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
-// RV32ZBC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV32ZBC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
-// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmulr.i32(i32 [[TMP0]], i32 [[TMP1]])
-// RV32ZBC-NEXT: ret i32 [[TMP2]]
-//
-uint32_t clmulr_32(uint32_t a, uint32_t b) {
- return __builtin_riscv_clmulr_32(a, b);
-}
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
deleted file mode 100644
index e44aa76083ad21..00000000000000
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
+++ /dev/null
@@ -1,24 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple riscv32 -target-feature +zbkc -emit-llvm %s -o - \
-// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
-// RUN: | FileCheck %s -check-prefix=RV32ZBKC
-
-#include <stdint.h>
-
-// RV32ZBKC-LABEL: @clmul_32(
-// RV32ZBKC-NEXT: entry:
-// RV32ZBKC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])
-// RV32ZBKC-NEXT: ret i32 [[TMP0]]
-//
-uint32_t clmul_32(uint32_t a, uint32_t b) {
- return __builtin_riscv_clmul_32(a, b);
-}
-
-// RV32ZBKC-LABEL: @clmulh_32(
-// RV32ZBKC-NEXT: entry:
-// RV32ZBKC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[A:%.*]], i32 [[B:%.*]])
-// RV32ZBKC-NEXT: ret i32 [[TMP0]]
-//
-uint32_t clmulh_32(uint32_t a, uint32_t b) {
- return __builtin_riscv_clmulh_32(a, b);
-}
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
deleted file mode 100644
index fd521622da8323..00000000000000
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple riscv32 -target-feature +zbkx -emit-llvm %s -o - \
-// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
-// RUN: | FileCheck %s -check-prefix=RV32ZBKX
-
-#include <stdint.h>
-
-// RV32ZBKX-LABEL: @xperm8(
-// RV32ZBKX-NEXT: entry:
-// RV32ZBKX-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.xperm8.i32(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
-// RV32ZBKX-NEXT: ret i32 [[TMP0]]
-//
-uint32_t xperm8(uint32_t rs1, uint32_t rs2)
-{
- return __builtin_riscv_xperm8_32(rs1, rs2);
-}
-
-// RV32ZBKX-LABEL: @xperm4(
-// RV32ZBKX-NEXT: entry:
-// RV32ZBKX-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.xperm4.i32(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
-// RV32ZBKX-NEXT: ret i32 [[TMP0]]
-//
-uint32_t xperm4(uint32_t rs1, uint32_t rs2)
-{
- return __builtin_riscv_xperm4_32(rs1, rs2);
-}
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
deleted file mode 100644
index db411427586307..00000000000000
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkb -emit-llvm %s -o - \
-// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
-// RUN: | FileCheck %s -check-prefix=RV64ZBKB
-
-#include <stdint.h>
-
-// RV64ZBKB-LABEL: @brev8_32(
-// RV64ZBKB-NEXT: entry:
-// RV64ZBKB-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[RS1:%.*]])
-// RV64ZBKB-NEXT: ret i32 [[TMP0]]
-//
-uint32_t brev8_32(uint32_t rs1)
-{
- return __builtin_riscv_brev8_32(rs1);
-}
-
-// RV64ZBKB-LABEL: @brev8_64(
-// RV64ZBKB-NEXT: entry:
-// RV64ZBKB-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.brev8.i64(i64 [[RS1:%.*]])
-// RV64ZBKB-NEXT: ret i64 [[TMP0]]
-//
-uint64_t brev8_64(uint64_t rs1)
-{
- return __builtin_riscv_brev8_64(rs1);
-}
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
deleted file mode 100644
index 93c1f7fcb761e7..00000000000000
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkx -emit-llvm %s -o - \
-// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
-// RUN: | FileCheck %s -check-prefix=RV64ZBKX
-
-#include <stdint.h>
-
-// RV64ZBKX-LABEL: @xperm8(
-// RV64ZBKX-NEXT: entry:
-// RV64ZBKX-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.xperm8.i64(i64 [[RS1:%.*]], i64 [[RS2:%.*]])
-// RV64ZBKX-NEXT: ret i64 [[TMP0]]
-//
-uint64_t xperm8(uint64_t rs1, uint64_t rs2)
-{
- return __builtin_riscv_xperm8_64(rs1, rs2);
-}
-
-// RV64ZBKX-LABEL: @xperm4(
-// RV64ZBKX-NEXT: entry:
-// RV64ZBKX-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.xperm4.i64(i64 [[RS1:%.*]], i64 [[RS2:%.*]])
-// RV64ZBKX-NEXT: ret i64 [[TMP0]]
-//
-uint64_t xperm4(uint64_t rs1, uint64_t rs2)
-{
- return __builtin_riscv_xperm4_64(rs1, rs2);
-}
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c
similarity index 70%
rename from clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
rename to clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c
index 37b2b4fcc35546..3a421f8c6cd421 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c
@@ -1,8 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zbb -emit-llvm %s -o - \
+// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
+// RUN: | FileCheck %s -check-prefix=RV32ZBB
// RUN: %clang_cc1 -triple riscv64 -target-feature +zbb -emit-llvm %s -o - \
// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
// RUN: | FileCheck %s -check-prefix=RV64ZBB
+// RV32ZBB-LABEL: @orc_b_32(
+// RV32ZBB-NEXT: entry:
+// RV32ZBB-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[A:%.*]])
+// RV32ZBB-NEXT: ret i32 [[TMP0]]
+//
// RV64ZBB-LABEL: @orc_b_32(
// RV64ZBB-NEXT: entry:
// RV64ZBB-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[A:%.*]])
@@ -12,6 +20,7 @@ unsigned int orc_b_32(unsigned int a) {
return __builtin_riscv_orc_b_32(a);
}
+#if __riscv_xlen == 64
// RV64ZBB-LABEL: @orc_b_64(
// RV64ZBB-NEXT: entry:
// RV64ZBB-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.orc.b.i64(i64 [[A:%.*]])
@@ -20,7 +29,13 @@ unsigned int orc_b_32(unsigned int a) {
unsigned long orc_b_64(unsigned long a) {
return __builtin_riscv_orc_b_64(a);
}
+#endif
+// RV32ZBB-LABEL: @clz_32(
+// RV32ZBB-NEXT: entry:
+// RV32ZBB-NEXT: [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[A:%.*]], i1 false)
+// RV32ZBB-NEXT: ret i32 [[TMP0]]
+//
// RV64ZBB-LABEL: @clz_32(
// RV64ZBB-NEXT: entry:
// RV64ZBB-NEXT: [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[A:%.*]], i1 false)
@@ -30,6 +45,7 @@ unsigned int clz_32(unsigned int a) {
return __builtin_riscv_clz_32(a);
}
+#if __riscv_xlen == 64
// RV64ZBB-LABEL: @clz_64(
// RV64ZBB-NEXT: entry:
// RV64ZBB-NEXT: [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[A:%.*]], i1 false)
@@ -39,7 +55,13 @@ unsigned int clz_32(unsigned int a) {
unsigned int clz_64(unsigned long a) {
return __builtin_riscv_clz_64(a);
}
+#endif
+// RV32ZBB-LABEL: @ctz_32(
+// RV32ZBB-NEXT: entry:
+// RV32ZBB-NEXT: [[TMP0:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 false)
+// RV32ZBB-NEXT: ret i32 [[TMP0]]
+//
// RV64ZBB-LABEL: @ctz_32(
// RV64ZBB-NEXT: entry:
// RV64ZBB-NEXT: [[TMP0:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 false)
@@ -49,6 +71,7 @@ unsigned int ctz_32(unsigned int a) {
return __builtin_riscv_ctz_32(a);
}
+#if __riscv_xlen == 64
// RV64ZBB-LABEL: @ctz_64(
// RV64ZBB-NEXT: entry:
// RV64ZBB-NEXT: [[TMP0:%.*]] = call i64 @llvm.cttz.i64(i64 [[A:%.*]], i1 false)
@@ -58,3 +81,4 @@ unsigned int ctz_32(unsigned int a) {
unsigned int ctz_64(unsigned long a) {
return __builtin_riscv_ctz_64(a);
}
+#endif
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c
similarity index 57%
rename from clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c
rename to clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c
index cf01063c4de0c6..aa5bebe38dd6b2 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbc.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c
@@ -1,9 +1,12 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zbc -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32ZBC
// RUN: %clang_cc1 -triple riscv64 -target-feature +zbc -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV64ZBC
#include <stdint.h>
+#if __riscv_xlen == 64
// RV64ZBC-LABEL: @clmul_64(
// RV64ZBC-NEXT: entry:
// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
@@ -48,7 +51,19 @@ uint64_t clmulh_64(uint64_t a, uint64_t b) {
uint64_t clmulr_64(uint64_t a, uint64_t b) {
return __builtin_riscv_clmulr_64(a, b);
}
+#endif
+// RV32ZBC-LABEL: @clmul_32(
+// RV32ZBC-NEXT: entry:
+// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV32ZBC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBC-NEXT: ret i32 [[TMP2]]
+//
// RV64ZBC-LABEL: @clmul_32(
// RV64ZBC-NEXT: entry:
// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
@@ -64,3 +79,34 @@ uint32_t clmul_32(uint32_t a, uint32_t b) {
return __builtin_riscv_clmul_32(a, b);
}
+#if __riscv_xlen == 32
+// RV32ZBC-LABEL: @clmulh_32(
+// RV32ZBC-NEXT: entry:
+// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV32ZBC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBC-NEXT: ret i32 [[TMP2]]
+//
+uint32_t clmulh_32(uint32_t a, uint32_t b) {
+ return __builtin_riscv_clmulh_32(a, b);
+}
+
+// RV32ZBC-LABEL: @clmulr_32(
+// RV32ZBC-NEXT: entry:
+// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV32ZBC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmulr.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV32ZBC-NEXT: ret i32 [[TMP2]]
+//
+uint32_t clmulr_32(uint32_t a, uint32_t b) {
+ return __builtin_riscv_clmulr_32(a, b);
+}
+#endif
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c
similarity index 56%
rename from clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
rename to clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c
index 78e3c7da4348eb..9be7cc6a0fb7ea 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c
@@ -2,19 +2,40 @@
// RUN: %clang_cc1 -triple riscv32 -target-feature +zbkb -emit-llvm %s -o - \
// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
// RUN: | FileCheck %s -check-prefix=RV32ZBKB
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkb -emit-llvm %s -o - \
+// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
+// RUN: | FileCheck %s -check-prefix=RV64ZBKB
#include <stdint.h>
-// RV32ZBKB-LABEL: @brev8(
+// RV32ZBKB-LABEL: @brev8_32(
// RV32ZBKB-NEXT: entry:
// RV32ZBKB-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[RS1:%.*]])
// RV32ZBKB-NEXT: ret i32 [[TMP0]]
//
-uint32_t brev8(uint32_t rs1)
+// RV64ZBKB-LABEL: @brev8_32(
+// RV64ZBKB-NEXT: entry:
+// RV64ZBKB-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[RS1:%.*]])
+// RV64ZBKB-NEXT: ret i32 [[TMP0]]
+//
+uint32_t brev8_32(uint32_t rs1)
{
return __builtin_riscv_brev8_32(rs1);
}
+#if __riscv_xlen == 64
+// RV64ZBKB-LABEL: @brev8_64(
+// RV64ZBKB-NEXT: entry:
+// RV64ZBKB-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.brev8.i64(i64 [[RS1:%.*]])
+// RV64ZBKB-NEXT: ret i64 [[TMP0]]
+//
+uint64_t brev8_64(uint64_t rs1)
+{
+ return __builtin_riscv_brev8_64(rs1);
+}
+#endif
+
+#if __riscv_xlen == 32
// RV32ZBKB-LABEL: @zip(
// RV32ZBKB-NEXT: entry:
// RV32ZBKB-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.zip.i32(i32 [[RS1:%.*]])
@@ -34,3 +55,4 @@ uint32_t unzip(uint32_t rs1)
{
return __builtin_riscv_unzip_32(rs1);
}
+#endif
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c
similarity index 60%
rename from clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
rename to clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c
index d133d434ccd7e3..ca09f899f9af62 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c
@@ -1,10 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zbkc -emit-llvm %s -o - \
+// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
+// RUN: | FileCheck %s -check-prefix=RV32ZBKC
// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkc -emit-llvm %s -o - \
// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
// RUN: | FileCheck %s -check-prefix=RV64ZBKC
#include <stdint.h>
+#if __riscv_xlen == 64
// RV64ZBKC-LABEL: @clmul_64(
// RV64ZBKC-NEXT: entry:
// RV64ZBKC-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[A:%.*]], i64 [[B:%.*]])
@@ -22,7 +26,13 @@ uint64_t clmul_64(uint64_t a, uint64_t b) {
uint64_t clmulh_64(uint64_t a, uint64_t b) {
return __builtin_riscv_clmulh_64(a, b);
}
+#endif
+// RV32ZBKC-LABEL: @clmul_32(
+// RV32ZBKC-NEXT: entry:
+// RV32ZBKC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+// RV32ZBKC-NEXT: ret i32 [[TMP0]]
+//
// RV64ZBKC-LABEL: @clmul_32(
// RV64ZBKC-NEXT: entry:
// RV64ZBKC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])
@@ -31,3 +41,14 @@ uint64_t clmulh_64(uint64_t a, uint64_t b) {
uint32_t clmul_32(uint32_t a, uint32_t b) {
return __builtin_riscv_clmul_32(a, b);
}
+
+#if __riscv_xlen == 32
+// RV32ZBKC-LABEL: @clmulh_32(
+// RV32ZBKC-NEXT: entry:
+// RV32ZBKC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[A:%.*]], i32 [[B:%.*]])
+// RV32ZBKC-NEXT: ret i32 [[TMP0]]
+//
+uint32_t clmulh_32(uint32_t a, uint32_t b) {
+ return __builtin_riscv_clmulh_32(a, b);
+}
+#endif
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c
new file mode 100644
index 00000000000000..1eeb2cc8582c69
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c
@@ -0,0 +1,53 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zbkx -emit-llvm %s -o - \
+// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
+// RUN: | FileCheck %s -check-prefix=RV32ZBKX
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkx -emit-llvm %s -o - \
+// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
+// RUN: | FileCheck %s -check-prefix=RV64ZBKX
+
+#include <stdint.h>
+
+#if __riscv_xlen == 32
+// RV32ZBKX-LABEL: @xperm8_32(
+// RV32ZBKX-NEXT: entry:
+// RV32ZBKX-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.xperm8.i32(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
+// RV32ZBKX-NEXT: ret i32 [[TMP0]]
+//
+uint32_t xperm8_32(uint32_t rs1, uint32_t rs2)
+{
+ return __builtin_riscv_xperm8_32(rs1, rs2);
+}
+
+// RV32ZBKX-LABEL: @xperm4_32(
+// RV32ZBKX-NEXT: entry:
+// RV32ZBKX-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.xperm4.i32(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
+// RV32ZBKX-NEXT: ret i32 [[TMP0]]
+//
+uint32_t xperm4_32(uint32_t rs1, uint32_t rs2)
+{
+ return __builtin_riscv_xperm4_32(rs1, rs2);
+}
+#endif
+
+#if __riscv_xlen == 64
+// RV64ZBKX-LABEL: @xperm8_64(
+// RV64ZBKX-NEXT: entry:
+// RV64ZBKX-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.xperm8.i64(i64 [[RS1:%.*]], i64 [[RS2:%.*]])
+// RV64ZBKX-NEXT: ret i64 [[TMP0]]
+//
+uint64_t xperm8_64(uint64_t rs1, uint64_t rs2)
+{
+ return __builtin_riscv_xperm8_64(rs1, rs2);
+}
+
+// RV64ZBKX-LABEL: @xperm4_64(
+// RV64ZBKX-NEXT: entry:
+// RV64ZBKX-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.xperm4.i64(i64 [[RS1:%.*]], i64 [[RS2:%.*]])
+// RV64ZBKX-NEXT: ret i64 [[TMP0]]
+//
+uint64_t xperm4_64(uint64_t rs1, uint64_t rs2)
+{
+ return __builtin_riscv_xperm4_64(rs1, rs2);
+}
+#endif
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