[clang] 244fd4d - [RISCV] Run mem2reg on more scalar C builtin tests to remove allocas and simplify checks. NFC

Craig Topper via cfe-commits cfe-commits at lists.llvm.org
Tue Aug 1 22:11:25 PDT 2023 

Author: Craig Topper
Date: 2023-08-01T22:10:54-07:00
New Revision: 244fd4dfc56a0d59655c65adac6a7258114b8af2

URL: https://github.com/llvm/llvm-project/commit/244fd4dfc56a0d59655c65adac6a7258114b8af2
DIFF: https://github.com/llvm/llvm-project/commit/244fd4dfc56a0d59655c65adac6a7258114b8af2.diff

LOG: [RISCV] Run mem2reg on more scalar C builtin tests to remove allocas and simplify checks. NFC

Added: 
    

Modified: 
    clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
    clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c

Removed: 
    


################################################################################
diff  --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
index 6e7ecf0300fba5..ffd869ce6d9b0a 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -1,14 +1,12 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv32 -target-feature +zbb -emit-llvm %s -o - \
+// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN:     | FileCheck %s  -check-prefix=RV32ZBB
 
 // RV32ZBB-LABEL: @orc_b_32(
 // RV32ZBB-NEXT:  entry:
-// RV32ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV32ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV32ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]])
-// RV32ZBB-NEXT:    ret i32 [[TMP1]]
+// RV32ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[A:%.*]])
+// RV32ZBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int orc_b_32(unsigned int a) {
   return __builtin_riscv_orc_b_32(a);
@@ -16,11 +14,8 @@ unsigned int orc_b_32(unsigned int a) {
 
 // RV32ZBB-LABEL: @clz_32(
 // RV32ZBB-NEXT:  entry:
-// RV32ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV32ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV32ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
-// RV32ZBB-NEXT:    ret i32 [[TMP1]]
+// RV32ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[A:%.*]], i1 false)
+// RV32ZBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
@@ -28,11 +23,8 @@ unsigned int clz_32(unsigned int a) {
 
 // RV32ZBB-LABEL: @ctz_32(
 // RV32ZBB-NEXT:  entry:
-// RV32ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV32ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV32ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV32ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
-// RV32ZBB-NEXT:    ret i32 [[TMP1]]
+// RV32ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 false)
+// RV32ZBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);

diff  --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
index 2309adfff84408..37b2b4fcc35546 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -1,14 +1,12 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zbb -emit-llvm %s -o - \
+// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
 // RUN:     | FileCheck %s  -check-prefix=RV64ZBB
 
 // RV64ZBB-LABEL: @orc_b_32(
 // RV64ZBB-NEXT:  entry:
-// RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV64ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV64ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV64ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]])
-// RV64ZBB-NEXT:    ret i32 [[TMP1]]
+// RV64ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[A:%.*]])
+// RV64ZBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int orc_b_32(unsigned int a) {
   return __builtin_riscv_orc_b_32(a);
@@ -16,11 +14,8 @@ unsigned int orc_b_32(unsigned int a) {
 
 // RV64ZBB-LABEL: @orc_b_64(
 // RV64ZBB-NEXT:  entry:
-// RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
-// RV64ZBB-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
-// RV64ZBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
-// RV64ZBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.orc.b.i64(i64 [[TMP0]])
-// RV64ZBB-NEXT:    ret i64 [[TMP1]]
+// RV64ZBB-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.orc.b.i64(i64 [[A:%.*]])
+// RV64ZBB-NEXT:    ret i64 [[TMP0]]
 //
 unsigned long orc_b_64(unsigned long a) {
   return __builtin_riscv_orc_b_64(a);
@@ -28,11 +23,8 @@ unsigned long orc_b_64(unsigned long a) {
 
 // RV64ZBB-LABEL: @clz_32(
 // RV64ZBB-NEXT:  entry:
-// RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV64ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV64ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV64ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
-// RV64ZBB-NEXT:    ret i32 [[TMP1]]
+// RV64ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[A:%.*]], i1 false)
+// RV64ZBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
@@ -40,11 +32,8 @@ unsigned int clz_32(unsigned int a) {
 
 // RV64ZBB-LABEL: @clz_64(
 // RV64ZBB-NEXT:  entry:
-// RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
-// RV64ZBB-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
-// RV64ZBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
-// RV64ZBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
-// RV64ZBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT:    [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[A:%.*]], i1 false)
+// RV64ZBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i32
 // RV64ZBB-NEXT:    ret i32 [[CAST]]
 //
 unsigned int clz_64(unsigned long a) {
@@ -53,11 +42,8 @@ unsigned int clz_64(unsigned long a) {
 
 // RV64ZBB-LABEL: @ctz_32(
 // RV64ZBB-NEXT:  entry:
-// RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
-// RV64ZBB-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
-// RV64ZBB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// RV64ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
-// RV64ZBB-NEXT:    ret i32 [[TMP1]]
+// RV64ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 false)
+// RV64ZBB-NEXT:    ret i32 [[TMP0]]
 //
 unsigned int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
@@ -65,11 +51,8 @@ unsigned int ctz_32(unsigned int a) {
 
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
-// RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
-// RV64ZBB-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
-// RV64ZBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
-// RV64ZBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false)
-// RV64ZBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT:    [[TMP0:%.*]] = call i64 @llvm.cttz.i64(i64 [[A:%.*]], i1 false)
+// RV64ZBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP0]] to i32
 // RV64ZBB-NEXT:    ret i32 [[CAST]]
 //
 unsigned int ctz_64(unsigned long a) {

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