[PATCH] D156779: [RISCV] Use correct LMUL!=1 types for __attribute__((riscv_rvv_vector_bits(N)))

[Wang Pengcheng via Phabricator via cfe-commits]

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We used to convert them to M1 <https://reviews.llvm.org/M1> types in arguments and return
value, which causes failures in CodeGen since it is not legal
to insert subvectors with LMUL>1 to M1 <https://reviews.llvm.org/M1> vectors.

Fixes 64266


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156779

Files:
  clang/lib/CodeGen/Targets/RISCV.cpp
  clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c

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