[PATCH] D154093: [clang-format] Break long strings in Verilog

[Owen Pan via Phabricator via cfe-commits]

owenpan added a comment.

In D154093#4542339 <https://reviews.llvm.org/D154093#4542339>, @sstwcw wrote:

> @owenpan What do you think about this revision especially the replacement part?

See D154093#4544495 <https://reviews.llvm.org/D154093#4544495>. Then we can extend it by using `,` instead of `+` for Verilog (plus inserting a pair of braces).


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D154093/new/

https://reviews.llvm.org/D154093