[clang] e56bf13 - [RISCV] Remove some instructions from Zvfbfwma by implying Zfbfmin according to the latest spec
Jun Sha via cfe-commits
cfe-commits at lists.llvm.org
Fri Jul 28 00:51:40 PDT 2023
Author: Jun Sha (Joshua)
Date: 2023-07-28T15:52:03+08:00
New Revision: e56bf133170c9fd49c91fe943ded26a3f2b30a04
URL: https://github.com/llvm/llvm-project/commit/e56bf133170c9fd49c91fe943ded26a3f2b30a04
DIFF: https://github.com/llvm/llvm-project/commit/e56bf133170c9fd49c91fe943ded26a3f2b30a04.diff
LOG: [RISCV] Remove some instructions from Zvfbfwma by implying Zfbfmin according to the latest spec
According to the latest spec, Zvfbfwma requires Zvfbfmin and Zvfbfmin requires Zfbfmin, with FLH/FSH/FMV.H.X/HMV.X.H removed from Zvfbfwma.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D155916
Added:
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rv64zhinx-invalid.s
llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
llvm/test/MC/RISCV/rvv/zvfbfwma.s
Removed:
################################################################################
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index edfc26c9dfcf37..3a0ab9431e0769 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -698,28 +698,28 @@
// CHECK-SSAIA-EXT: __riscv_ssaia 1000000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32izfbfmin0p6 -x c -E -dM %s \
+// RUN: -march=rv32izfbfmin0p8 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFBFMIN-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64izfbfmin0p6 -x c -E -dM %s \
+// RUN: -march=rv64izfbfmin0p8 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFBFMIN-EXT %s
-// CHECK-ZFBFMIN-EXT: __riscv_zfbfmin 6000{{$}}
+// CHECK-ZFBFMIN-EXT: __riscv_zfbfmin 8000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32ifzvfbfmin0p6 -x c -E -dM %s \
+// RUN: -march=rv32ifzvfbfmin0p8 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64ifzvfbfmin0p6 -x c -E -dM %s \
+// RUN: -march=rv64ifzvfbfmin0p8 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s
-// CHECK-ZVFBFMIN-EXT: __riscv_zvfbfmin 6000{{$}}
+// CHECK-ZVFBFMIN-EXT: __riscv_zvfbfmin 8000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32ifzvfbfwma0p6 -x c -E -dM %s \
+// RUN: -march=rv32ifzvfbfwma0p8 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64ifzvfbfwma0p6 -x c -E -dM %s \
+// RUN: -march=rv64ifzvfbfwma0p8 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s
-// CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 6000{{$}}
+// CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 8000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
// RUN: -march=rv32iv_zvbb1p0_zvkned1p0_zvknhb1p0_zvkt1p0 -x c -E -dM %s -o - \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index b9f9138f2404c9..07c750770d32fc 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -199,7 +199,7 @@ The primary goal of experimental support is to assist in the process of ratifica
LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20230131-c0b298a/zfa-20230414.pdf>`__.
``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
- LLVM implements assembler support for the `0.6.9 draft specification <https://github.com/riscv/riscv-bfloat16/releases/tag/20230614>`_.
+ LLVM implements assembler support for the `0.8.0 draft specification <https://github.com/riscv/riscv-bfloat16/releases/tag/20230629>`_.
``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1>`__.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index f0bae51ec1edf9..21605a4085ee3a 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -163,7 +163,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zacas", RISCVExtensionVersion{1, 0}},
{"zfa", RISCVExtensionVersion{0, 2}},
- {"zfbfmin", RISCVExtensionVersion{0, 6}},
+ {"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicond", RISCVExtensionVersion{1, 0}},
@@ -174,8 +174,8 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zvbb", RISCVExtensionVersion{1, 0}},
{"zvbc", RISCVExtensionVersion{1, 0}},
- {"zvfbfmin", RISCVExtensionVersion{0, 6}},
- {"zvfbfwma", RISCVExtensionVersion{0, 6}},
+ {"zvfbfmin", RISCVExtensionVersion{0, 8}},
+ {"zvfbfwma", RISCVExtensionVersion{0, 8}},
// vector crypto
{"zvkg", RISCVExtensionVersion{1, 0}},
@@ -978,8 +978,8 @@ static const char *ImpliedExtsZve32x[] = {"zvl32b", "zicsr"};
static const char *ImpliedExtsZve64d[] = {"zve64f", "d"};
static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
-static const char *ImpliedExtsZvfbfmin[] = {"zve32f"};
-static const char *ImpliedExtsZvfbfwma[] = {"zve32f"};
+static const char *ImpliedExtsZvfbfmin[] = {"zve32f", "zfbfmin"};
+static const char *ImpliedExtsZvfbfwma[] = {"zvfbfmin"};
static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"};
static const char *ImpliedExtsZvkn[] = {"zvbb", "zvkned", "zvknhb", "zvkt"};
static const char *ImpliedExtsZvknc[] = {"zvbc", "zvkn"};
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 51c2986ea87a21..414fd24e5a744c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -461,10 +461,18 @@ def HasVInstructionsF64 : Predicate<"Subtarget->hasVInstructionsF64()">;
def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMultiply()">;
+def FeatureStdExtZfbfmin
+ : SubtargetFeature<"experimental-zfbfmin", "HasStdExtZfbfmin", "true",
+ "'Zfbfmin' (Scalar BF16 Converts)",
+ [FeatureStdExtF]>;
+def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
+ AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
+ "'Zfbfmin' (Scalar BF16 Converts)">;
+
def FeatureStdExtZvfbfmin
: SubtargetFeature<"experimental-zvfbfmin", "HasStdExtZvfbfmin", "true",
"'Zvbfmin' (Vector BF16 Converts)",
- [FeatureStdExtZve32f]>;
+ [FeatureStdExtZve32f, FeatureStdExtZfbfmin]>;
def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
"'Zvfbfmin' (Vector BF16 Converts)">;
@@ -472,7 +480,7 @@ def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
def FeatureStdExtZvfbfwma
: SubtargetFeature<"experimental-zvfbfwma", "HasStdExtZvfbfwma", "true",
"'Zvfbfwma' (Vector BF16 widening mul-add)",
- [FeatureStdExtZve32f]>;
+ [FeatureStdExtZvfbfmin]>;
def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
"'Zvfbfwma' (Vector BF16 widening mul-add)">;
@@ -659,22 +667,13 @@ def FeatureStdExtSsaia
"excluding the machine-level CSRs and behavior not "
"directly visible to supervisor level.)", []>;
-def FeatureStdExtZfbfmin
- : SubtargetFeature<"experimental-zfbfmin", "HasStdExtZfbfmin", "true",
- "'Zfbfmin' (Scalar BF16 Converts)",
- [FeatureStdExtF]>;
-def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
- AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
- "'Zfbfmin' (Scalar BF16 Converts)">;
-
def HasHalfFPLoadStoreMove
: Predicate<"Subtarget->hasHalfFPLoadStoreMove()">,
AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin,
- FeatureStdExtZfbfmin, FeatureStdExtZvfbfwma),
+ FeatureStdExtZfbfmin),
"'Zfh' (Half-Precision Floating-Point) or "
"'Zfhmin' (Half-Precision Floating-Point Minimal) or "
- "'Zfbfmin' (Scalar BF16 Converts) or "
- "'Zvfbfwma' (Vector BF16 widening mul-add)">;
+ "'Zfbfmin' (Scalar BF16 Converts)">;
def FeatureStdExtZacas
: SubtargetFeature<"experimental-zacas", "HasStdExtZacas", "true",
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index f51c0f74473a0d..8ec87f6cfc8e6b 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -124,8 +124,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
return hasStdExtZfhOrZfhmin() || hasStdExtZhinxOrZhinxmin();
}
bool hasHalfFPLoadStoreMove() const {
- return HasStdExtZfh || HasStdExtZfhmin || HasStdExtZfbfmin ||
- HasStdExtZvfbfwma;
+ return HasStdExtZfh || HasStdExtZfhmin || HasStdExtZfbfmin;
}
bool is64Bit() const { return IsRV64; }
MVT getXLenVT() const { return XLenVT; }
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index b0d5925ec36aa6..94fef910c3f7aa 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -254,9 +254,9 @@
; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
-; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p6"
-; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
-; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0"
+; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8"
+; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
+; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
; RV64M: .attribute 5, "rv64i2p1_m2p0"
@@ -341,9 +341,9 @@
; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
-; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p6"
-; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
-; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0"
+; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8"
+; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
+; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0"
define i32 @addi(i32 %a) {
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 91df42449c4cca..bb3cb0bb9c5718 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -270,14 +270,14 @@
.attribute arch, "rv32i_ssaia1p0"
# CHECK: attribute 5, "rv32i2p1_ssaia1p0"
-.attribute arch, "rv32i_zfbfmin0p6"
-# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p6"
+.attribute arch, "rv32i_zfbfmin0p8"
+# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8"
-.attribute arch, "rv32i_zvfbfmin0p6"
-# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
+.attribute arch, "rv32i_zvfbfmin0p8"
+# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
-.attribute arch, "rv32i_zvfbfwma0p6"
-# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0"
+.attribute arch, "rv32i_zvfbfwma0p8"
+# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
.attribute arch, "rv64i_xsfcie"
# CHECK: attribute 5, "rv64i2p1_xsfcie1p0"
diff --git a/llvm/test/MC/RISCV/rv64zhinx-invalid.s b/llvm/test/MC/RISCV/rv64zhinx-invalid.s
index 5c447754d6cde8..a49056c6a7629c 100644
--- a/llvm/test/MC/RISCV/rv64zhinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zhinx-invalid.s
@@ -1,7 +1,7 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s
# Not support float registers
-flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
# Invalid instructions
fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s b/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
index 44b486242fb8a4..dfe4bb6a15e550 100644
--- a/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
@@ -1,7 +1,7 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+zhinxmin %s 2>&1 | FileCheck %s
# Not support float registers
-flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
# Invalid instructions
fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rvv/zvfbfwma.s b/llvm/test/MC/RISCV/rvv/zvfbfwma.s
index ed577bca2d7401..c3eefe6ca89c78 100644
--- a/llvm/test/MC/RISCV/rvv/zvfbfwma.s
+++ b/llvm/test/MC/RISCV/rvv/zvfbfwma.s
@@ -45,24 +45,24 @@ vfwmaccbf16.vf v8, fa0, v4
# CHECK-INST: flh ft0, 12(a0)
# CHECK-ENCODING: [0x07,0x10,0xc5,0x00]
-# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
# CHECK-UNKNOWN: 07 10 c5 00 <unknown>
flh f0, 12(a0)
# CHECK-INST: fsh ft6, 2047(s4)
# CHECK-ENCODING: [0xa7,0x1f,0x6a,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
# CHECK-UNKNOWN: a7 1f 6a 7e <unknown>
fsh f6, 2047(s4)
# CHECK-INST: fmv.x.h a2, fs7
# CHECK-ENCODING: [0x53,0x86,0x0b,0xe4]
-# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
# CHECK-UNKNOWN: 53 86 0b e4 <unknown>
fmv.x.h a2, fs7
# CHECK-INST: fmv.h.x ft1, a6
# CHECK-ENCODING: [0xd3,0x00,0x08,0xf4]
-# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
# CHECK-UNKNOWN: d3 00 08 f4 <unknown>
fmv.h.x ft1, a6
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