[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948
-  // TODO: The 'q' extension requires rv64.
-  // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
 
----------------
craig.topper wrote:
> asb wrote:
> > imkiva wrote:
> > > wangpc wrote:
> > > > I think the comment is outdated here. `E` can be combined with all other extensions according to spec:
> > > > > Unless otherwise stated, standard extensions compatible with RV32I and RV64I are also compatible with RV32E and RV64E, respectively.
> > > > And, please see also D70401 for more context.
> > > I downloaded the specification from [here](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf), and in page 34 the footnote says:
> > > 
> > > > RV32E can be combined with all current standard extensions. Defining the F, D, and Q extensions as having a 16-entry floating point register file when combined with RV32E was considered but **decided against**. To support systems with reduced floating-point register state, we intend to define a “Zfinx” extension...
> > > 
> > > It seems in the spec version 20191213, they rejected the combination of `E` with standard floating-point extensions, instead, a separate extension `Zfinx` is chosen for the original purpose.
> > > I am not sure if there's any newer specification that decides to allow this combination.
> > > 
> > > 
> > There's a link to the ratified version on https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions - see https://drive.google.com/file/d/1GjHmphVKvJlOBJydAt36g0Oc8yCOPtKw/view
> > 
> > As @wangpc says, the restriction was removed and so the comment is out of date.
> > RV32E can be combined with all current standard extensions. Defining the F, D, and Q extensions as having a 16-entry floating point register file when combined with RV32E was considered but decided against. To support systems with reduced floating-point register state, we intend to define a “Zfinx” extension...
> 
> That really only says that the register file for F and D is still 32 entries with RV32E. It doesn't say they are incompatible. Maybe there was some even older text?
There was older text removed here https://github.com/riscv/riscv-isa-manual/commit/4845f5d61f96a827ec4d21d2c5a80b6bf7881e56


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