[PATCH] D144829: [BPF] Add a few new insns under cpu=v4

[Yonghong Song via Phabricator via cfe-commits]

yonghong-song updated this revision to Diff 543709.
yonghong-song added a comment.

Three major changes in this patch:

- for ldsx insns, remove 32bit ldsx insns (1-byte and 2-byte sign extension) since the ldsx insn expects to sign extension all the way up to 8-byte and normal 32bit insn (e.g. BPF_ALU) expects to zero out the top bits. Instead do a ldbsx/ldhsx and then take the lower 4 byte to extract 32bit value. This also resolved one disasm issue reported by Eduard.
- for movsx insn, for 32bit sign extenstion to 64bit. Match both "sext_inreg GPR:$src, i32" (left and right shifting) and "sext GPR32:$src".
- Add an internal flag to control when to generate gotol insns in BPFMIPeephole.cpp. This permits a simpler test for gotol insns.

With the above changes, the following change is needed:

  diff --git a/tools/testing/selftests/bpf/progs/verifier_movsx.c b/tools/testing/selftests/bpf/progs/verifier_movsx.c
  index 5ee7d004f8ba..e27bfa11c9b3 100644
  --- a/tools/testing/selftests/bpf/progs/verifier_movsx.c
  +++ b/tools/testing/selftests/bpf/progs/verifier_movsx.c
  @@ -59,7 +59,7 @@ __naked void mov64sx_s32(void)
   {
          asm volatile ("                                 \
          r0 = 0xfffffffe;                                \
  -       r0 = (s32)w0;                                   \
  +       r0 = (s32)r0;                                   \
          r0 >>= 1;                                       \
          exit;                                           \
   "      ::: __clobber_all);
  @@ -181,7 +181,7 @@ __naked void mov64sx_s32_range(void)
   {
          asm volatile ("                                 \
          call %[bpf_get_prandom_u32];                    \
  -       r1 = (s32)w0;                                   \
  +       r1 = (s32)r0;                                   \
          /* r1 with s32 range */                         \
          if r1 s> 0x7fffffff goto l0_%=;                 \
          if r1 s< -0x80000000 goto l0_%=;                \

in order to compile kernel cpu v4 support (patch series v3)

  https://lore.kernel.org/bpf/20230720000103.99949-1-yhs@fb.com/

I will update the kernel side once we resolved all llvm issues.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144829/new/

https://reviews.llvm.org/D144829

Files:
  clang/lib/Basic/Targets/BPF.cpp
  clang/lib/Basic/Targets/BPF.h
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
  llvm/lib/Target/BPF/BPF.td
  llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFISelLowering.h
  llvm/lib/Target/BPF/BPFInstrFormats.td
  llvm/lib/Target/BPF/BPFInstrInfo.td
  llvm/lib/Target/BPF/BPFMIPeephole.cpp
  llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
  llvm/lib/Target/BPF/BPFSubtarget.cpp
  llvm/lib/Target/BPF/BPFSubtarget.h
  llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCFixups.h
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
  llvm/test/CodeGen/BPF/assembler-disassembler-v4.s
  llvm/test/CodeGen/BPF/bswap.ll
  llvm/test/CodeGen/BPF/gotol.ll
  llvm/test/CodeGen/BPF/ldsx.ll
  llvm/test/CodeGen/BPF/movsx.ll
  llvm/test/CodeGen/BPF/sdiv_smod.ll

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