[PATCH] D144829: [BPF] Add a few new insns under cpu=v4

[Yonghong Song via Phabricator via cfe-commits]

yonghong-song added a comment.

In D144829#4519036 <https://reviews.llvm.org/D144829#4519036>, @eddyz87 wrote:

> I tried adding a test similar to `assemble-disassemble.ll`:
>
>   // RUN: llvm-mc -triple bpfel --mcpu=v4 --assemble --filetype=obj %s \
>   // RUN:   | llvm-objdump -d --mattr=+alu32 - \
>   // RUN:   | FileCheck %s
>   
>   // CHECK: d7 01 00 00 10 00 00 00	r1 = bswap16 r1
>   // CHECK: d7 02 00 00 20 00 00 00	r2 = bswap32 r2
>   // CHECK: d7 03 00 00 40 00 00 00	r3 = bswap64 r3
>   r1 = bswap16 r1
>   r2 = bswap32 r2
>   r3 = bswap64 r3
>   
>   // CHECK: 91 41 00 00 00 00 00 00	r1 = *(s8 *)(r4 + 0x0)
>   // CHECK: 89 52 04 00 00 00 00 00	r2 = *(s16 *)(r5 + 0x4)
>   // CHECK: 81 63 08 00 00 00 00 00	r3 = *(s32 *)(r6 + 0x8)
>   r1 = *(s8 *)(r4 + 0)
>   r2 = *(s16 *)(r5 + 4)
>   r3 = *(s32 *)(r6 + 8)
>   
>   // CHECK: 91 41 00 00 00 00 00 00	w1 = *(s8 *)(r4 + 0x0)
>   // CHECK: 89 52 04 00 00 00 00 00	w2 = *(s16 *)(r5 + 0x4)
>   w1 = *(s8 *)(r4 + 0)
>   w2 = *(s16 *)(r5 + 4)
>   
>   // CHECK: bf 41 08 00 00 00 00 00	r1 = (s8)r4
>   // CHECK: bf 52 10 00 00 00 00 00	r2 = (s16)r5
>   // CHECK: bf 63 20 00 00 00 00 00	r3 = (s32)w6
>   r1 = (s8)r4
>   r2 = (s16)r5
>   r3 = (s32)w6
>   // Should this work as well: r3 = (s32)r6 ?
>   
>   // CHECK: bc 31 08 00 00 00 00 00	w1 = (s8)w3
>   // CHECK: bc 42 10 00 00 00 00 00	w2 = (s16)w4
>   w1 = (s8)w3
>   w2 = (s16)w4
>   
>   // CHECK: 3f 31 01 00 00 00 00 00	r1 s/= r3
>   // CHECK: 9f 42 01 00 00 00 00 00	r2 s%= r4
>   r1 s/= r3
>   r2 s%= r4
>   
>   // CHECK: 3c 31 01 00 00 00 00 00	w1 s/= w3
>   // CHECK: 9c 42 01 00 00 00 00 00	w2 s%= w4
>   w1 s/= w3
>   w2 s%= w4
>
> And it looks like some instructions are not printed correctly:
>
>   $ llvm-mc -triple bpfel --mcpu=v4 --assemble --filetype=obj /home/eddy/work/llvm-project/llvm/test/CodeGen/BPF/assembler-disassembler-v4.s | llvm-objdump -d --mattr=+alu32 -
>   
>   <stdin>:	file format elf64-bpf
>   
>   Disassembly of section .text:
>   
>   0000000000000000 <.text>:
>          0:	d7 01 00 00 10 00 00 00	r1 = bswap16 r1
>          1:	d7 02 00 00 20 00 00 00	r2 = bswap32 r2
>          2:	d7 03 00 00 40 00 00 00	r3 = bswap64 r3
>          3:	91 41 00 00 00 00 00 00	w1 = *(s8 *)(r4 + 0x0)
>          4:	89 52 04 00 00 00 00 00	w2 = *(s16 *)(r5 + 0x4)
>          5:	81 63 08 00 00 00 00 00	<unknown>
>          6:	91 41 00 00 00 00 00 00	w1 = *(s8 *)(r4 + 0x0)
>          7:	89 52 04 00 00 00 00 00	w2 = *(s16 *)(r5 + 0x4)
>          8:	bf 41 08 00 00 00 00 00	r1 = (s8)r4
>          9:	bf 52 10 00 00 00 00 00	r2 = (s16)r5
>         10:	bf 63 20 00 00 00 00 00	r3 = (s32)w6
>         11:	bc 31 08 00 00 00 00 00	w1 = (s8)w3
>         12:	bc 42 10 00 00 00 00 00	w2 = (s16)w4
>         13:	3f 31 01 00 00 00 00 00	r1 s/= r3
>         14:	9f 42 01 00 00 00 00 00	r2 s%= r4
>         15:	3c 31 01 00 00 00 00 00	w1 s/= w3
>         16:	9c 42 01 00 00 00 00 00	w2 s%= w4
>
> I'm not sure if this is an issue with disassembler or some additional `--mattr` options are needed.

There is a problem in the td file for 32-bit signed load. Current definition is not quite right since it is supposed to sign-extension all the way to 64bit. I will fix it in the next revision.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144829/new/

https://reviews.llvm.org/D144829