[clang] 14b466b - [X86] Fix a typo of Broadwell after D74918. NFC

Fangrui Song via cfe-commits cfe-commits at lists.llvm.org
Sun Jul 23 15:15:09 PDT 2023


Author: Fangrui Song
Date: 2023-07-23T15:15:05-07:00
New Revision: 14b466b940c674dc225b6dd2fd05c2faebcc11d5

URL: https://github.com/llvm/llvm-project/commit/14b466b940c674dc225b6dd2fd05c2faebcc11d5
DIFF: https://github.com/llvm/llvm-project/commit/14b466b940c674dc225b6dd2fd05c2faebcc11d5.diff

LOG: [X86] Fix a typo of Broadwell after D74918. NFC

Close #64053

Added: 
    

Modified: 
    clang/lib/Basic/Targets/X86.cpp

Removed: 
    


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diff  --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 26b89619b2c94b..5e28d20be3d3f5 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -1365,7 +1365,7 @@ bool X86TargetInfo::validateAsmConstraint(
 // | Sandy Bridge                       |                      64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html                                                                    |
 // | Ivy Bridge                         |                      64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html                                                      |
 // | Haswell                            |                      64 | https://www.7-cpu.com/cpu/Haswell.html                                                                                                                       |
-// | Boadwell                           |                      64 | https://www.7-cpu.com/cpu/Broadwell.html                                                                                                                     |
+// | Broadwell                          |                      64 | https://www.7-cpu.com/cpu/Broadwell.html                                                                                                                     |
 // | Skylake (including skylake-avx512) |                      64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy"                                                                       |
 // | Cascade Lake                       |                      64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy"                                                                  |
 // | Skylake                            |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy"                                                                           |


        


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