[clang] c6f66de - [X86] Add SM3 instructions.
Freddy Ye via cfe-commits
cfe-commits at lists.llvm.org
Wed Jul 19 19:24:36 PDT 2023
Author: Freddy Ye
Date: 2023-07-20T10:24:16+08:00
New Revision: c6f66de21af060ead6e5402858351e9e869dc15f
URL: https://github.com/llvm/llvm-project/commit/c6f66de21af060ead6e5402858351e9e869dc15f
DIFF: https://github.com/llvm/llvm-project/commit/c6f66de21af060ead6e5402858351e9e869dc15f.diff
LOG: [X86] Add SM3 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Reviewed By: pengfei
Differential Revision: https://reviews.llvm.org/D155147
Added:
clang/lib/Headers/sm3intrin.h
clang/test/CodeGen/X86/sm3-builtins.c
clang/test/CodeGen/X86/sm3-error.c
llvm/test/CodeGen/X86/sm3-intrinsics.ll
llvm/test/MC/Disassembler/X86/sm3-32.txt
llvm/test/MC/Disassembler/X86/sm3-64.txt
llvm/test/MC/X86/sm3-att-32.s
llvm/test/MC/X86/sm3-att-64.s
llvm/test/MC/X86/sm3-intel-32.s
llvm/test/MC/X86/sm3-intel-64.s
Modified:
clang/docs/ReleaseNotes.rst
clang/include/clang/Basic/BuiltinsX86.def
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/X86.cpp
clang/lib/Basic/Targets/X86.h
clang/lib/Headers/CMakeLists.txt
clang/lib/Headers/immintrin.h
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/attr-target-x86.c
clang/test/Driver/x86-target-features.c
clang/test/Preprocessor/x86_target_features.c
llvm/docs/ReleaseNotes.rst
llvm/include/llvm/IR/IntrinsicsX86.td
llvm/include/llvm/TargetParser/X86TargetParser.def
llvm/lib/Target/X86/X86.td
llvm/lib/Target/X86/X86InstrInfo.td
llvm/lib/Target/X86/X86InstrSSE.td
llvm/lib/TargetParser/Host.cpp
llvm/lib/TargetParser/X86TargetParser.cpp
llvm/test/TableGen/x86-fold-tables.inc
Removed:
################################################################################
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 21d8e34a25e804..bce9e2ab3eba82 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -817,6 +817,10 @@ X86 Support
* Support intrinsic of ``_mm256_sha512msg1_epi64``.
* Support intrinsic of ``_mm256_sha512msg2_epi64``.
* Support intrinsic of ``_mm256_sha512rnds2_epi64``.
+- Support ISA of ``SM3``.
+ * Support intrinsic of ``_mm_sm3msg1_epi32``.
+ * Support intrinsic of ``_mm_sm3msg2_epi32``.
+ * Support intrinsic of ``_mm_sm3rnds2_epi32``.
Arm and AArch64 Support
^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/clang/include/clang/Basic/BuiltinsX86.def b/clang/include/clang/Basic/BuiltinsX86.def
index fd4f769994a999..7fe19d86a256bd 100644
--- a/clang/include/clang/Basic/BuiltinsX86.def
+++ b/clang/include/clang/Basic/BuiltinsX86.def
@@ -2146,6 +2146,11 @@ TARGET_HEADER_BUILTIN(_InterlockedIncrement64, "WiWiD*", "nh", INTRIN_H, ALL
TARGET_HEADER_BUILTIN(_InterlockedOr64, "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(_InterlockedXor64, "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
+// SM3
+TARGET_BUILTIN(__builtin_ia32_vsm3msg1, "V4UiV4UiV4UiV4Ui", "nV:128:", "sm3")
+TARGET_BUILTIN(__builtin_ia32_vsm3msg2, "V4UiV4UiV4UiV4Ui", "nV:128:", "sm3")
+TARGET_BUILTIN(__builtin_ia32_vsm3rnds2, "V4UiV4UiV4UiV4UiIUi", "nV:128:", "sm3")
+
#undef BUILTIN
#undef TARGET_BUILTIN
#undef TARGET_HEADER_BUILTIN
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index df5c091cf12db1..0aede381ec6dc8 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5058,6 +5058,8 @@ def msha : Flag<["-"], "msha">, Group<m_x86_Features_Group>;
def mno_sha : Flag<["-"], "mno-sha">, Group<m_x86_Features_Group>;
def msha512 : Flag<["-"], "msha512">, Group<m_x86_Features_Group>;
def mno_sha512 : Flag<["-"], "mno-sha512">, Group<m_x86_Features_Group>;
+def msm3 : Flag<["-"], "msm3">, Group<m_x86_Features_Group>;
+def mno_sm3 : Flag<["-"], "mno-sm3">, Group<m_x86_Features_Group>;
def mtbm : Flag<["-"], "mtbm">, Group<m_x86_Features_Group>;
def mno_tbm : Flag<["-"], "mno-tbm">, Group<m_x86_Features_Group>;
def mtsxldtrk : Flag<["-"], "mtsxldtrk">, Group<m_x86_Features_Group>;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index b09ec21f77dbed..dc56b89c6b6078 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -265,6 +265,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasSHA512 = true;
} else if (Feature == "+shstk") {
HasSHSTK = true;
+ } else if (Feature == "+sm3") {
+ HasSM3 = true;
} else if (Feature == "+movbe") {
HasMOVBE = true;
} else if (Feature == "+sgx") {
@@ -776,6 +778,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__SHSTK__");
if (HasSGX)
Builder.defineMacro("__SGX__");
+ if (HasSM3)
+ Builder.defineMacro("__SM3__");
if (HasPREFETCHI)
Builder.defineMacro("__PREFETCHI__");
if (HasPREFETCHWT1)
@@ -1005,6 +1009,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
.Case("sha", true)
.Case("sha512", true)
.Case("shstk", true)
+ .Case("sm3", true)
.Case("sse", true)
.Case("sse2", true)
.Case("sse3", true)
@@ -1111,6 +1116,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("sha", HasSHA)
.Case("sha512", HasSHA512)
.Case("shstk", HasSHSTK)
+ .Case("sm3", HasSM3)
.Case("sse", SSELevel >= SSE1)
.Case("sse2", SSELevel >= SSE2)
.Case("sse3", SSELevel >= SSE3)
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index e7bc2d7ef3f61a..f0b8864d855249 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -114,6 +114,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
bool HasSHA = false;
bool HasSHA512 = false;
bool HasSHSTK = false;
+ bool HasSM3 = false;
bool HasSGX = false;
bool HasCX8 = false;
bool HasCX16 = false;
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index 44fb2bb899264c..f09edc72b22d6a 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -205,6 +205,7 @@ set(x86_files
sgxintrin.h
sha512intrin.h
shaintrin.h
+ sm3intrin.h
smmintrin.h
tbmintrin.h
tmmintrin.h
diff --git a/clang/lib/Headers/immintrin.h b/clang/lib/Headers/immintrin.h
index e8dcdc95b22bad..ecdbef158107e6 100644
--- a/clang/lib/Headers/immintrin.h
+++ b/clang/lib/Headers/immintrin.h
@@ -274,6 +274,11 @@
#include <sha512intrin.h>
#endif
+#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \
+ defined(__SM3__)
+#include <sm3intrin.h>
+#endif
+
#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \
defined(__RDPID__)
/// Returns the value of the IA32_TSC_AUX MSR (0xc0000103).
diff --git a/clang/lib/Headers/sm3intrin.h b/clang/lib/Headers/sm3intrin.h
new file mode 100644
index 00000000000000..8a3d8bc9ef0149
--- /dev/null
+++ b/clang/lib/Headers/sm3intrin.h
@@ -0,0 +1,238 @@
+/*===-------------------- sm3intrin.h - SM3 intrinsics ---------------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __IMMINTRIN_H
+#error "Never use <sm3intrin.h> directly; include <immintrin.h> instead."
+#endif // __IMMINTRIN_H
+
+#ifndef __SM3INTRIN_H
+#define __SM3INTRIN_H
+
+#define __DEFAULT_FN_ATTRS128 \
+ __attribute__((__always_inline__, __nodebug__, __target__("sm3"), \
+ __min_vector_width__(128)))
+
+/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
+/// intrinsic performs an initial calculation for the next four SM3 message
+/// words. The calculated results are stored in \a dst.
+///
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m128i _mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C)
+/// \endcode
+///
+/// This intrinsic corresponds to the \c VSM3MSG1 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [4 x int].
+/// \param __B
+/// A 128-bit vector of [4 x int].
+/// \param __C
+/// A 128-bit vector of [4 x int].
+/// \returns
+/// A 128-bit vector of [4 x int].
+///
+/// \code{.operation}
+/// DEFINE ROL32(dword, n) {
+/// count := n % 32
+/// dest := (dword << count) | (dword >> (32 - count))
+/// RETURN dest
+/// }
+/// DEFINE P1(x) {
+/// RETURN x ^ ROL32(x, 15) ^ ROL32(x, 23)
+/// }
+/// W[0] := __C.dword[0]
+/// W[1] := __C.dword[1]
+/// W[2] := __C.dword[2]
+/// W[3] := __C.dword[3]
+/// W[7] := __A.dword[0]
+/// W[8] := __A.dword[1]
+/// W[9] := __A.dword[2]
+/// W[10] := __A.dword[3]
+/// W[13] := __B.dword[0]
+/// W[14] := __B.dword[1]
+/// W[15] := __B.dword[2]
+/// TMP0 := W[7] ^ W[0] ^ ROL32(W[13], 15)
+/// TMP1 := W[8] ^ W[1] ^ ROL32(W[14], 15)
+/// TMP2 := W[9] ^ W[2] ^ ROL32(W[15], 15)
+/// TMP3 := W[10] ^ W[3]
+/// dst.dword[0] := P1(TMP0)
+/// dst.dword[1] := P1(TMP1)
+/// dst.dword[2] := P1(TMP2)
+/// dst.dword[3] := P1(TMP3)
+/// dst[MAX:128] := 0
+/// \endcode
+static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg1_epi32(__m128i __A,
+ __m128i __B,
+ __m128i __C) {
+ return (__m128i)__builtin_ia32_vsm3msg1((__v4su)__A, (__v4su)__B,
+ (__v4su)__C);
+}
+
+/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
+/// intrinsic performs the final calculation for the next four SM3 message
+/// words. The calculated results are stored in \a dst.
+///
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m128i _mm_sm3msg2_epi32(__m128i __A, __m128i __B, __m128i __C)
+/// \endcode
+///
+/// This intrinsic corresponds to the \c VSM3MSG2 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [4 x int].
+/// \param __B
+/// A 128-bit vector of [4 x int].
+/// \param __C
+/// A 128-bit vector of [4 x int].
+/// \returns
+/// A 128-bit vector of [4 x int].
+///
+/// \code{.operation}
+/// DEFINE ROL32(dword, n) {
+/// count := n % 32
+/// dest := (dword << count) | (dword >> (32-count))
+/// RETURN dest
+/// }
+/// WTMP[0] := __A.dword[0]
+/// WTMP[1] := __A.dword[1]
+/// WTMP[2] := __A.dword[2]
+/// WTMP[3] := __A.dword[3]
+/// W[3] := __B.dword[0]
+/// W[4] := __B.dword[1]
+/// W[5] := __B.dword[2]
+/// W[6] := __B.dword[3]
+/// W[10] := __C.dword[0]
+/// W[11] := __C.dword[1]
+/// W[12] := __C.dword[2]
+/// W[13] := __C.dword[3]
+/// W[16] := ROL32(W[3], 7) ^ W[10] ^ WTMP[0]
+/// W[17] := ROL32(W[4], 7) ^ W[11] ^ WTMP[1]
+/// W[18] := ROL32(W[5], 7) ^ W[12] ^ WTMP[2]
+/// W[19] := ROL32(W[6], 7) ^ W[13] ^ WTMP[3]
+/// W[19] := W[19] ^ ROL32(W[16], 6) ^ ROL32(W[16], 15) ^ ROL32(W[16], 30)
+/// dst.dword[0] := W[16]
+/// dst.dword[1] := W[17]
+/// dst.dword[2] := W[18]
+/// dst.dword[3] := W[19]
+/// dst[MAX:128] := 0
+/// \endcode
+static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg2_epi32(__m128i __A,
+ __m128i __B,
+ __m128i __C) {
+ return (__m128i)__builtin_ia32_vsm3msg2((__v4su)__A, (__v4su)__B,
+ (__v4su)__C);
+}
+
+/// This intrinsic performs two rounds of SM3 operation using initial SM3 state
+/// (C, D, G, H) from \a __A, an initial SM3 states (A, B, E, F)
+/// from \a __B and a pre-computed words from the \a __C. \a __A with
+/// initial SM3 state of (C, D, G, H) assumes input of non-rotated left
+/// variables from previous state. The updated SM3 state (A, B, E, F) is
+/// written to \a __A. The \a imm8 should contain the even round number
+/// for the first of the two rounds computed by this instruction. The
+/// computation masks the \a imm8 value by AND’ing it with 0x3E so that only
+/// even round numbers from 0 through 62 are used for this operation. The
+/// calculated results are stored in \a dst.
+///
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m128i _mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C, const int
+/// imm8) \endcode
+///
+/// This intrinsic corresponds to the \c VSM3RNDS2 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [4 x int].
+/// \param __B
+/// A 128-bit vector of [4 x int].
+/// \param __C
+/// A 128-bit vector of [4 x int].
+/// \param imm8
+/// A 8-bit constant integer.
+/// \returns
+/// A 128-bit vector of [4 x int].
+///
+/// \code{.operation}
+/// DEFINE ROL32(dword, n) {
+/// count := n % 32
+/// dest := (dword << count) | (dword >> (32-count))
+/// RETURN dest
+/// }
+/// DEFINE P0(dword) {
+/// RETURN dword ^ ROL32(dword, 9) ^ ROL32(dword, 17)
+/// }
+/// DEFINE FF(x,y,z, round){
+/// IF round < 16
+/// RETURN (x ^ y ^ z)
+/// ELSE
+/// RETURN (x & y) | (x & z) | (y & z)
+/// FI
+/// }
+/// DEFINE GG(x, y, z, round){
+/// IF round < 16
+/// RETURN (x ^ y ^ z)
+/// ELSE
+/// RETURN (x & y) | (~x & z)
+/// FI
+/// }
+/// A[0] := __B.dword[3]
+/// B[0] := __B.dword[2]
+/// C[0] := __A.dword[3]
+/// D[0] := __A.dword[2]
+/// E[0] := __B.dword[1]
+/// F[0] := __B.dword[0]
+/// G[0] := __A.dword[1]
+/// H[0] := __A.dword[0]
+/// W[0] := __C.dword[0]
+/// W[1] := __C.dword[1]
+/// W[4] := __C.dword[2]
+/// W[5] := __C.dword[3]
+/// C[0] := ROL32(C[0], 9)
+/// D[0] := ROL32(D[0], 9)
+/// G[0] := ROL32(G[0], 19)
+/// H[0] := ROL32(H[0], 19)
+/// ROUND := __D & 0x3E
+/// IF ROUND < 16
+/// CONST := 0x79CC4519
+/// ELSE
+/// CONST := 0x7A879D8A
+/// FI
+/// CONST := ROL32(CONST,ROUND)
+/// FOR i:= 0 to 1
+/// S1 := ROL32((ROL32(A[i], 12) + E[i] + CONST), 7)
+/// S2 := S1 ^ ROL32(A[i], 12)
+/// T1 := FF(A[i], B[i], C[i], ROUND) + D[i] + S2 + (W[i] ^ W[i+4])
+/// T2 := GG(E[i], F[i], G[i], ROUND) + H[i] + S1 + W[i]
+/// D[i+1] := C[i]
+/// C[i+1] := ROL32(B[i],9)
+/// B[i+1] := A[i]
+/// A[i+1] := T1
+/// H[i+1] := G[i]
+/// G[i+1] := ROL32(F[i], 19)
+/// F[i+1] := E[i]
+/// E[i+1] := P0(T2)
+/// CONST := ROL32(CONST, 1)
+/// ENDFOR
+/// dst.dword[3] := A[2]
+/// dst.dword[2] := B[2]
+/// dst.dword[1] := E[2]
+/// dst.dword[0] := F[2]
+/// dst[MAX:128] := 0
+/// \endcode
+#define _mm_sm3rnds2_epi32(A, B, C, D) \
+ (__m128i) __builtin_ia32_vsm3rnds2((__v4su)A, (__v4su)B, (__v4su)C, (int)D)
+
+#undef __DEFAULT_FN_ATTRS128
+
+#endif // __SM3INTRIN_H
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 228095bfbd2248..077f560d4fe1bb 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -6296,6 +6296,7 @@ bool Sema::CheckX86BuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
case X86::BI__builtin_ia32_pternlogq128_maskz:
case X86::BI__builtin_ia32_pternlogq256_mask:
case X86::BI__builtin_ia32_pternlogq256_maskz:
+ case X86::BI__builtin_ia32_vsm3rnds2:
i = 3; l = 0; u = 255;
break;
case X86::BI__builtin_ia32_gatherpfdpd:
diff --git a/clang/test/CodeGen/X86/sm3-builtins.c b/clang/test/CodeGen/X86/sm3-builtins.c
new file mode 100644
index 00000000000000..fb703ccfae6723
--- /dev/null
+++ b/clang/test/CodeGen/X86/sm3-builtins.c
@@ -0,0 +1,22 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +sm3 -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +sm3 -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include <immintrin.h>
+
+__m128i test_mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C) {
+ // CHECK-LABEL: @test_mm_sm3msg1_epi32(
+ // CHECK: call <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
+ return _mm_sm3msg1_epi32(__A, __B, __C);
+}
+
+__m128i test_mm_sm3msg2_epi32(__m128i __A, __m128i __B, __m128i __C) {
+ // CHECK-LABEL: @test_mm_sm3msg2_epi32(
+ // CHECK: call <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}})
+ return _mm_sm3msg2_epi32(__A, __B, __C);
+}
+
+__m128i test_mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C) {
+ // CHECK-LABEL: @test_mm_sm3rnds2_epi32(
+ // CHECK: call <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 127)
+ return _mm_sm3rnds2_epi32(__A, __B, __C, 127);
+}
diff --git a/clang/test/CodeGen/X86/sm3-error.c b/clang/test/CodeGen/X86/sm3-error.c
new file mode 100644
index 00000000000000..230ebe7036beb0
--- /dev/null
+++ b/clang/test/CodeGen/X86/sm3-error.c
@@ -0,0 +1,7 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=i686-unknown-unknown -target-feature +sm3 -emit-llvm -fsyntax-only -verify
+
+#include <immintrin.h>
+
+__m128i test_mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C) {
+ return _mm_sm3rnds2_epi32(__A, __B, __C, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
diff --git a/clang/test/CodeGen/attr-target-x86.c b/clang/test/CodeGen/attr-target-x86.c
index d4a1732aad041c..f55fac1f5e885d 100644
--- a/clang/test/CodeGen/attr-target-x86.c
+++ b/clang/test/CodeGen/attr-target-x86.c
@@ -54,9 +54,9 @@ void __attribute__((target("arch=x86-64-v4"))) x86_64_v4(void) {}
// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" "tune-cpu"="i686"
// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
// CHECK-NOT: tune-cpu
-// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sha512,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686"
+// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sha512,-sm3,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686"
// CHECK: #3 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+crc32,+cx8,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" "tune-cpu"="i686"
-// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sha512,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686"
+// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sha512,-sm3,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686"
// CHECK: #5 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes,-vaes"
// CHECK-NOT: tune-cpu
// CHECK: #6 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-3dnow,-3dnowa,-mmx"
diff --git a/clang/test/Driver/x86-target-features.c b/clang/test/Driver/x86-target-features.c
index b811e23ced4b7f..2d86fc9c8901d4 100644
--- a/clang/test/Driver/x86-target-features.c
+++ b/clang/test/Driver/x86-target-features.c
@@ -354,6 +354,11 @@
// SHA512: "-target-feature" "+sha512"
// NO-SHA512: "-target-feature" "-sha512"
+// RUN: %clang --target=i386 -msm3 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=SM3 %s
+// RUN: %clang --target=i386 -mno-sm3 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-SM3 %s
+// SM3: "-target-feature" "+sm3"
+// NO-SM3: "-target-feature" "-sm3"
+
// RUN: %clang --target=i386 -march=i386 -mcrc32 %s -### 2>&1 | FileCheck -check-prefix=CRC32 %s
// RUN: %clang --target=i386 -march=i386 -mno-crc32 %s -### 2>&1 | FileCheck -check-prefix=NO-CRC32 %s
// CRC32: "-target-feature" "+crc32"
diff --git a/clang/test/Preprocessor/x86_target_features.c b/clang/test/Preprocessor/x86_target_features.c
index 0972997342678d..6095a1b7d9233b 100644
--- a/clang/test/Preprocessor/x86_target_features.c
+++ b/clang/test/Preprocessor/x86_target_features.c
@@ -673,6 +673,20 @@
// SHA512NOAVX-NOT: #define __AVX__ 1
// SHA512NOAVX-NOT: #define __SHA512__ 1
+// RUN: %clang -target i686-unknown-linux-gnu -march=atom -msm3 -x c -E -dM -o - %s | FileCheck -check-prefix=SM3 %s
+
+// SM3: #define __AVX__ 1
+// SM3: #define __SM3__ 1
+
+// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mno-sm3 -x c -E -dM -o - %s | FileCheck -check-prefix=NOSM3 %s
+
+// NOSM3-NOT: #define __SM3__ 1
+
+// RUN: %clang -target i686-unknown-linux-gnu -march=atom -msm3 -mno-avx -x c -E -dM -o - %s | FileCheck -check-prefix=SM3NOAVX %s
+
+// SM3NOAVX-NOT: #define __SM3__ 1
+// SM3NOAVX-NOT: #define __AVX__ 1
+
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mcrc32 -x c -E -dM -o - %s | FileCheck -check-prefix=CRC32 %s
// CRC32: #define __CRC32__ 1
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 74a9eb1eb73a2f..bf016730d32f48 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -280,6 +280,7 @@ Changes to the X86 Backend
``X86CmovConversion`` pass now respects this builtin and does not convert CMOVs to branches.
* Add support for the ``PBNDKB`` instruction.
* Support ISA of ``SHA512``.
+* Support ISA of ``SM3``.
Changes to the OCaml bindings
-----------------------------
diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td
index b60675a85910a9..0f7bc83bfb23a6 100644
--- a/llvm/include/llvm/IR/IntrinsicsX86.td
+++ b/llvm/include/llvm/IR/IntrinsicsX86.td
@@ -5527,6 +5527,25 @@ def int_x86_vcvtneps2bf16256
DefaultAttrsIntrinsic<[llvm_v8bf16_ty], [llvm_v8f32_ty], [IntrNoMem]>;
}
//===----------------------------------------------------------------------===//
+// SM3 intrinsics
+let TargetPrefix = "x86" in {
+ def int_x86_vsm3msg1
+ : ClangBuiltin<"__builtin_ia32_vsm3msg1">,
+ DefaultAttrsIntrinsic<[llvm_v4i32_ty],
+ [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+ [IntrNoMem]>;
+ def int_x86_vsm3msg2
+ : ClangBuiltin<"__builtin_ia32_vsm3msg2">,
+ DefaultAttrsIntrinsic<[llvm_v4i32_ty],
+ [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+ [IntrNoMem]>;
+ def int_x86_vsm3rnds2
+ : ClangBuiltin<"__builtin_ia32_vsm3rnds2">,
+ DefaultAttrsIntrinsic<[llvm_v4i32_ty],
+ [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty],
+ [ImmArg<ArgIndex<3>>, IntrNoMem]>;
+}
+//===----------------------------------------------------------------------===//
// RAO-INT intrinsics
let TargetPrefix = "x86" in {
def int_x86_aadd32
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def
index 0e3008bf6ca128..8febef092b4986 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.def
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -221,6 +221,7 @@ X86_FEATURE (XSAVES, "xsaves")
X86_FEATURE (HRESET, "hreset")
X86_FEATURE (RAOINT, "raoint")
X86_FEATURE (AVX512FP16, "avx512fp16")
+X86_FEATURE (SM3, "sm3")
X86_FEATURE (AMX_FP16, "amx-fp16")
X86_FEATURE (CMPCCXADD, "cmpccxadd")
X86_FEATURE (AVXNECONVERT, "avxneconvert")
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 5abbcea3f8681a..2eedf542adffd7 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -245,6 +245,9 @@ def FeatureSHA512 : SubtargetFeature<"sha512", "HasSHA512", "true",
// using Shadow Stack
def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true",
"Support CET Shadow-Stack instructions">;
+def FeatureSM3 : SubtargetFeature<"sm3", "HasSM3", "true",
+ "Support SM3 instructions",
+ [FeatureAVX]>;
def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
"Support PRFCHW instructions">;
def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 5cd230f346f9d1..6a2d0bcf2ed38c 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -969,6 +969,7 @@ def HasADX : Predicate<"Subtarget->hasADX()">;
def HasSHA : Predicate<"Subtarget->hasSHA()">;
def HasSHA512 : Predicate<"Subtarget->hasSHA512()">;
def HasSGX : Predicate<"Subtarget->hasSGX()">;
+def HasSM3 : Predicate<"Subtarget->hasSM3()">;
def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">;
def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">;
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 5ed77a1c16b382..b63d8107e6e33d 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -8317,3 +8317,44 @@ def VSHA512RNDS2rr : I<0xcb, MRMSrcReg, (outs VR256:$dst),
(int_x86_vsha512rnds2 VR256:$src1, VR256:$src2, VR128:$src3))]>,
VEX_L, VEX_4V, T8XD, Sched<[WriteVecIMul]>;
}
+
+// FIXME: Is there a better scheduler class for SM3 than WriteVecIMul?
+let Predicates = [HasSM3], Constraints = "$src1 = $dst" in {
+ multiclass SM3_Base<string OpStr> {
+ def rr : I<0xda, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, VR128:$src3),
+ !strconcat(OpStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ [(set VR128:$dst,
+ (!cast<Intrinsic>("int_x86_"#OpStr) VR128:$src1,
+ VR128:$src2, VR128:$src3))]>,
+ Sched<[WriteVecIMul]>, VEX_4V;
+ def rm : I<0xda, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, i128mem:$src3),
+ !strconcat(OpStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ [(set VR128:$dst,
+ (!cast<Intrinsic>("int_x86_"#OpStr) VR128:$src1,
+ VR128:$src2, (loadv4i32 addr:$src3)))]>,
+ Sched<[WriteVecIMul]>, VEX_4V;
+ }
+
+ multiclass VSM3RNDS2_Base {
+ def rr : Ii8<0xde, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, VR128:$src3, i32u8imm:$src4),
+ "vsm3rnds2\t{$src4, $src3, $src2, $dst|$dst, $src2, $src3, $src4}",
+ [(set VR128:$dst,
+ (int_x86_vsm3rnds2 VR128:$src1,
+ VR128:$src2, VR128:$src3, timm:$src4))]>,
+ Sched<[WriteVecIMul]>;
+ def rm : Ii8<0xde, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, i128mem:$src3, i32u8imm:$src4),
+ "vsm3rnds2\t{$src4, $src3, $src2, $dst|$dst, $src2, $src3, $src4}",
+ [(set VR128:$dst,
+ (int_x86_vsm3rnds2 VR128:$src1,
+ VR128:$src2, (loadv4i32 addr:$src3), timm:$src4))]>,
+ Sched<[WriteVecIMul]>;
+ }
+}
+
+defm VSM3MSG1 : SM3_Base<"vsm3msg1">, T8PS;
+defm VSM3MSG2 : SM3_Base<"vsm3msg2">, T8PD;
+defm VSM3RNDS2 : VSM3RNDS2_Base, VEX_4V, TAPD;
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 378dac9c5f02c8..5cf66c145cac73 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -1747,6 +1747,7 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
bool HasLeaf7Subleaf1 =
MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
Features["sha512"] = HasLeaf7Subleaf1 && ((EAX >> 0) & 1);
+ Features["sm3"] = HasLeaf7Subleaf1 && ((EAX >> 1) & 1);
Features["raoint"] = HasLeaf7Subleaf1 && ((EAX >> 3) & 1);
Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index 39f03aa05c470d..91182f4433f242 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -613,6 +613,7 @@ constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
+constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX;
// AVX512 features.
constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
diff --git a/llvm/test/CodeGen/X86/sm3-intrinsics.ll b/llvm/test/CodeGen/X86/sm3-intrinsics.ll
new file mode 100644
index 00000000000000..bab30f6deea7e8
--- /dev/null
+++ b/llvm/test/CodeGen/X86/sm3-intrinsics.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sm3 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sm3 | FileCheck %s
+
+define <4 x i32> @test_int_x86_vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
+; CHECK-LABEL: test_int_x86_vsm3msg1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsm3msg1 %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x70,0xda,0xc2]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
+ ret <4 x i32> %ret
+}
+declare <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
+
+define <4 x i32> @test_int_x86_vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
+; CHECK-LABEL: test_int_x86_vsm3msg2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsm3msg2 %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x71,0xda,0xc2]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
+ ret <4 x i32> %ret
+}
+declare <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
+
+define <4 x i32> @test_int_x86_vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
+; CHECK-LABEL: test_int_x86_vsm3rnds2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsm3rnds2 $127, %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe3,0x71,0xde,0xc2,0x7f]
+; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
+ %ret = call <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32 127)
+ ret <4 x i32> %ret
+}
+declare <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32 %D)
+
diff --git a/llvm/test/MC/Disassembler/X86/sm3-32.txt b/llvm/test/MC/Disassembler/X86/sm3-32.txt
new file mode 100644
index 00000000000000..d34a1581aa11ed
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/sm3-32.txt
@@ -0,0 +1,87 @@
+# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: vsm3msg1 %xmm4, %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmm4
+0xc4,0xe2,0x60,0xda,0xd4
+
+# ATT: vsm3msg1 268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10
+
+# ATT: vsm3msg1 291(%edi,%eax,4), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00
+
+# ATT: vsm3msg1 (%eax), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [eax]
+0xc4,0xe2,0x60,0xda,0x10
+
+# ATT: vsm3msg1 -512(,%ebp,2), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT: vsm3msg1 2032(%ecx), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032]
+0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00
+
+# ATT: vsm3msg1 -2048(%edx), %xmm3, %xmm2
+# INTEL: vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048]
+0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff
+
+# ATT: vsm3msg2 %xmm4, %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmm4
+0xc4,0xe2,0x61,0xda,0xd4
+
+# ATT: vsm3msg2 268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10
+
+# ATT: vsm3msg2 291(%edi,%eax,4), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00
+
+# ATT: vsm3msg2 (%eax), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [eax]
+0xc4,0xe2,0x61,0xda,0x10
+
+# ATT: vsm3msg2 -512(,%ebp,2), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT: vsm3msg2 2032(%ecx), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032]
+0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00
+
+# ATT: vsm3msg2 -2048(%edx), %xmm3, %xmm2
+# INTEL: vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048]
+0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff
+
+# ATT: vsm3rnds2 $123, %xmm4, %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmm4, 123
+0xc4,0xe3,0x61,0xde,0xd4,0x7b
+
+# ATT: vsm3rnds2 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vsm3rnds2 $123, 291(%edi,%eax,4), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vsm3rnds2 $123, (%eax), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123
+0xc4,0xe3,0x61,0xde,0x10,0x7b
+
+# ATT: vsm3rnds2 $123, -512(,%ebp,2), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b
+
+# ATT: vsm3rnds2 $123, 2032(%ecx), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123
+0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b
+
+# ATT: vsm3rnds2 $123, -2048(%edx), %xmm3, %xmm2
+# INTEL: vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123
+0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b
+
diff --git a/llvm/test/MC/Disassembler/X86/sm3-64.txt b/llvm/test/MC/Disassembler/X86/sm3-64.txt
new file mode 100644
index 00000000000000..177b2fea10854e
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/sm3-64.txt
@@ -0,0 +1,87 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: vsm3msg1 %xmm4, %xmm13, %xmm12
+# INTEL: vsm3msg1 xmm12, xmm13, xmm4
+0xc4,0x62,0x10,0xda,0xe4
+
+# ATT: vsm3msg1 268435456(%rbp,%r14,8), %xmm13, %xmm12
+# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10
+
+# ATT: vsm3msg1 291(%r8,%rax,4), %xmm13, %xmm12
+# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00
+
+# ATT: vsm3msg1 (%rip), %xmm13, %xmm12
+# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00
+
+# ATT: vsm3msg1 -512(,%rbp,2), %xmm13, %xmm12
+# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT: vsm3msg1 2032(%rcx), %xmm13, %xmm12
+# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00
+
+# ATT: vsm3msg1 -2048(%rdx), %xmm13, %xmm12
+# INTEL: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff
+
+# ATT: vsm3msg2 %xmm4, %xmm13, %xmm12
+# INTEL: vsm3msg2 xmm12, xmm13, xmm4
+0xc4,0x62,0x11,0xda,0xe4
+
+# ATT: vsm3msg2 268435456(%rbp,%r14,8), %xmm13, %xmm12
+# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10
+
+# ATT: vsm3msg2 291(%r8,%rax,4), %xmm13, %xmm12
+# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00
+
+# ATT: vsm3msg2 (%rip), %xmm13, %xmm12
+# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00
+
+# ATT: vsm3msg2 -512(,%rbp,2), %xmm13, %xmm12
+# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT: vsm3msg2 2032(%rcx), %xmm13, %xmm12
+# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00
+
+# ATT: vsm3msg2 -2048(%rdx), %xmm13, %xmm12
+# INTEL: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff
+
+# ATT: vsm3rnds2 $123, %xmm4, %xmm13, %xmm12
+# INTEL: vsm3rnds2 xmm12, xmm13, xmm4, 123
+0xc4,0x63,0x11,0xde,0xe4,0x7b
+
+# ATT: vsm3rnds2 $123, 268435456(%rbp,%r14,8), %xmm13, %xmm12
+# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vsm3rnds2 $123, 291(%r8,%rax,4), %xmm13, %xmm12
+# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vsm3rnds2 $123, (%rip), %xmm13, %xmm12
+# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
+0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vsm3rnds2 $123, -512(,%rbp,2), %xmm13, %xmm12
+# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [2*rbp - 512], 123
+0xc4,0x63,0x11,0xde,0x24,0x6d,0x00,0xfe,0xff,0xff,0x7b
+
+# ATT: vsm3rnds2 $123, 2032(%rcx), %xmm13, %xmm12
+# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rcx + 2032], 123
+0xc4,0x63,0x11,0xde,0xa1,0xf0,0x07,0x00,0x00,0x7b
+
+# ATT: vsm3rnds2 $123, -2048(%rdx), %xmm13, %xmm12
+# INTEL: vsm3rnds2 xmm12, xmm13, xmmword ptr [rdx - 2048], 123
+0xc4,0x63,0x11,0xde,0xa2,0x00,0xf8,0xff,0xff,0x7b
+
diff --git a/llvm/test/MC/X86/sm3-att-32.s b/llvm/test/MC/X86/sm3-att-32.s
new file mode 100644
index 00000000000000..19ff6ed3965908
--- /dev/null
+++ b/llvm/test/MC/X86/sm3-att-32.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
+ vsm3msg1 %xmm4, %xmm3, %xmm2
+
+// CHECK: vsm3msg1 268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+ vsm3msg1 268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK: vsm3msg1 291(%edi,%eax,4), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+ vsm3msg1 291(%edi,%eax,4), %xmm3, %xmm2
+
+// CHECK: vsm3msg1 (%eax), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x10]
+ vsm3msg1 (%eax), %xmm3, %xmm2
+
+// CHECK: vsm3msg1 -512(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg1 -512(,%ebp,2), %xmm3, %xmm2
+
+// CHECK: vsm3msg1 2032(%ecx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
+ vsm3msg1 2032(%ecx), %xmm3, %xmm2
+
+// CHECK: vsm3msg1 -2048(%edx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
+ vsm3msg1 -2048(%edx), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
+ vsm3msg2 %xmm4, %xmm3, %xmm2
+
+// CHECK: vsm3msg2 268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+ vsm3msg2 268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 291(%edi,%eax,4), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+ vsm3msg2 291(%edi,%eax,4), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 (%eax), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x10]
+ vsm3msg2 (%eax), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 -512(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg2 -512(,%ebp,2), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 2032(%ecx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
+ vsm3msg2 2032(%ecx), %xmm3, %xmm2
+
+// CHECK: vsm3msg2 -2048(%edx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
+ vsm3msg2 -2048(%edx), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
+ vsm3rnds2 $123, %xmm4, %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vsm3rnds2 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, 291(%edi,%eax,4), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vsm3rnds2 $123, 291(%edi,%eax,4), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, (%eax), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x10,0x7b]
+ vsm3rnds2 $123, (%eax), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, -512(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vsm3rnds2 $123, -512(,%ebp,2), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, 2032(%ecx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b]
+ vsm3rnds2 $123, 2032(%ecx), %xmm3, %xmm2
+
+// CHECK: vsm3rnds2 $123, -2048(%edx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b]
+ vsm3rnds2 $123, -2048(%edx), %xmm3, %xmm2
+
diff --git a/llvm/test/MC/X86/sm3-att-64.s b/llvm/test/MC/X86/sm3-att-64.s
new file mode 100644
index 00000000000000..e9ffd489b2b5af
--- /dev/null
+++ b/llvm/test/MC/X86/sm3-att-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 %xmm4, %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4]
+ vsm3msg1 %xmm4, %xmm13, %xmm12
+
+// CHECK: vsm3msg1 268435456(%rbp,%r14,8), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+ vsm3msg1 268435456(%rbp,%r14,8), %xmm13, %xmm12
+
+// CHECK: vsm3msg1 291(%r8,%rax,4), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+ vsm3msg1 291(%r8,%rax,4), %xmm13, %xmm12
+
+// CHECK: vsm3msg1 (%rip), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00]
+ vsm3msg1 (%rip), %xmm13, %xmm12
+
+// CHECK: vsm3msg1 -512(,%rbp,2), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg1 -512(,%rbp,2), %xmm13, %xmm12
+
+// CHECK: vsm3msg1 2032(%rcx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00]
+ vsm3msg1 2032(%rcx), %xmm13, %xmm12
+
+// CHECK: vsm3msg1 -2048(%rdx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff]
+ vsm3msg1 -2048(%rdx), %xmm13, %xmm12
+
+// CHECK: vsm3msg2 %xmm4, %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4]
+ vsm3msg2 %xmm4, %xmm13, %xmm12
+
+// CHECK: vsm3msg2 268435456(%rbp,%r14,8), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+ vsm3msg2 268435456(%rbp,%r14,8), %xmm13, %xmm12
+
+// CHECK: vsm3msg2 291(%r8,%rax,4), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+ vsm3msg2 291(%r8,%rax,4), %xmm13, %xmm12
+
+// CHECK: vsm3msg2 (%rip), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00]
+ vsm3msg2 (%rip), %xmm13, %xmm12
+
+// CHECK: vsm3msg2 -512(,%rbp,2), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg2 -512(,%rbp,2), %xmm13, %xmm12
+
+// CHECK: vsm3msg2 2032(%rcx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00]
+ vsm3msg2 2032(%rcx), %xmm13, %xmm12
+
+// CHECK: vsm3msg2 -2048(%rdx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff]
+ vsm3msg2 -2048(%rdx), %xmm13, %xmm12
+
+// CHECK: vsm3rnds2 $123, %xmm4, %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b]
+ vsm3rnds2 $123, %xmm4, %xmm13, %xmm12
+
+// CHECK: vsm3rnds2 $123, 268435456(%rbp,%r14,8), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vsm3rnds2 $123, 268435456(%rbp,%r14,8), %xmm13, %xmm12
+
+// CHECK: vsm3rnds2 $123, 291(%r8,%rax,4), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vsm3rnds2 $123, 291(%r8,%rax,4), %xmm13, %xmm12
+
+// CHECK: vsm3rnds2 $123, (%rip), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b]
+ vsm3rnds2 $123, (%rip), %xmm13, %xmm12
+
+// CHECK: vsm3rnds2 $123, -512(,%rbp,2), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x24,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vsm3rnds2 $123, -512(,%rbp,2), %xmm13, %xmm12
+
+// CHECK: vsm3rnds2 $123, 2032(%rcx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa1,0xf0,0x07,0x00,0x00,0x7b]
+ vsm3rnds2 $123, 2032(%rcx), %xmm13, %xmm12
+
+// CHECK: vsm3rnds2 $123, -2048(%rdx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa2,0x00,0xf8,0xff,0xff,0x7b]
+ vsm3rnds2 $123, -2048(%rdx), %xmm13, %xmm12
+
diff --git a/llvm/test/MC/X86/sm3-intel-32.s b/llvm/test/MC/X86/sm3-intel-32.s
new file mode 100644
index 00000000000000..da3818a1dc9974
--- /dev/null
+++ b/llvm/test/MC/X86/sm3-intel-32.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple i686-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
+ vsm3msg1 xmm2, xmm3, xmm4
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [eax]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x10]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [eax]
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [ecx + 2032]
+
+// CHECK: vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
+ vsm3msg1 xmm2, xmm3, xmmword ptr [edx - 2048]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
+ vsm3msg2 xmm2, xmm3, xmm4
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [eax]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x10]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [eax]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [ecx + 2032]
+
+// CHECK: vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
+ vsm3msg2 xmm2, xmm3, xmmword ptr [edx - 2048]
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmm4, 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x10,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [eax], 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x91,0xf0,0x07,0x00,0x00,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [ecx + 2032], 123
+
+// CHECK: vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0x92,0x00,0xf8,0xff,0xff,0x7b]
+ vsm3rnds2 xmm2, xmm3, xmmword ptr [edx - 2048], 123
+
diff --git a/llvm/test/MC/X86/sm3-intel-64.s b/llvm/test/MC/X86/sm3-intel-64.s
new file mode 100644
index 00000000000000..3325544388373d
--- /dev/null
+++ b/llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4]
+ vsm3msg1 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+ vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+ vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00]
+ vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00]
+ vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff]
+ vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4]
+ vsm3msg2 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+ vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+ vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00]
+ vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+ vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00]
+ vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff]
+ vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmm4, 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b]
+ vsm3rnds2 xmm12, xmm13, xmm4, 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b]
+ vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [2*rbp - 512], 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x24,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vsm3rnds2 xmm12, xmm13, xmmword ptr [2*rbp - 512], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rcx + 2032], 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa1,0xf0,0x07,0x00,0x00,0x7b]
+ vsm3rnds2 xmm12, xmm13, xmmword ptr [rcx + 2032], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rdx - 2048], 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xa2,0x00,0xf8,0xff,0xff,0x7b]
+ vsm3rnds2 xmm12, xmm13, xmmword ptr [rdx - 2048], 123
+
diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc
index 1cb6b51c79ea95..ded55969826ec7 100644
--- a/llvm/test/TableGen/x86-fold-tables.inc
+++ b/llvm/test/TableGen/x86-fold-tables.inc
@@ -4800,6 +4800,9 @@ static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
{X86::VSHUFPSZ128rrikz, X86::VSHUFPSZ128rmikz, 0},
{X86::VSHUFPSZ256rrikz, X86::VSHUFPSZ256rmikz, 0},
{X86::VSHUFPSZrrikz, X86::VSHUFPSZrmikz, 0},
+ {X86::VSM3MSG1rr, X86::VSM3MSG1rm, 0},
+ {X86::VSM3MSG2rr, X86::VSM3MSG2rm, 0},
+ {X86::VSM3RNDS2rr, X86::VSM3RNDS2rm, 0},
{X86::VSQRTPDZ128rk, X86::VSQRTPDZ128mk, 0},
{X86::VSQRTPDZ256rk, X86::VSQRTPDZ256mk, 0},
{X86::VSQRTPDZrk, X86::VSQRTPDZmk, 0},
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