[clang] df71216 - [RISCV] Make __builtin_riscv_clz/ctz return an unsigned int instead of signed int.

[Craig Topper via cfe-commits]

Author: Craig Topper
Date: 2023-07-14T11:13:47-07:00
New Revision: df71216d0301780de9dfc467745dd10843de4400

URL: https://github.com/llvm/llvm-project/commit/df71216d0301780de9dfc467745dd10843de4400
DIFF: https://github.com/llvm/llvm-project/commit/df71216d0301780de9dfc467745dd10843de4400.diff

LOG: [RISCV] Make __builtin_riscv_clz/ctz return an unsigned int instead of signed int.

This is different than the target independent __builtin_clz/ctz, but
logically makes more sense.

Added: 
    

Modified: 
    clang/include/clang/Basic/BuiltinsRISCV.def
    clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
    clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
    clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
    clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c

Removed: 
    


################################################################################
diff  --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def
index 4b4c7858d0fa7d..8eac0afae3ec95 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.def
+++ b/clang/include/clang/Basic/BuiltinsRISCV.def
@@ -18,10 +18,10 @@
 // Zbb extension
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "UZiUZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "UWiUWi", "nc", "zbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_clz_32, "iUZi", "nc", "zbb|xtheadbb")
-TARGET_BUILTIN(__builtin_riscv_clz_64, "iUWi", "nc", "zbb|xtheadbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_ctz_32, "iUZi", "nc", "zbb")
-TARGET_BUILTIN(__builtin_riscv_ctz_64, "iUWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_clz_32, "UiUZi", "nc", "zbb|xtheadbb")
+TARGET_BUILTIN(__builtin_riscv_clz_64, "UiUWi", "nc", "zbb|xtheadbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_ctz_32, "UiUZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_ctz_64, "UiUWi", "nc", "zbb,64bit")
 
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")

diff  --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
index 915dd806d21791..a16b1436fef9c7 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
@@ -10,7 +10,7 @@
 // RV32XTHEADBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
 // RV32XTHEADBB-NEXT:    ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+unsigned int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -23,6 +23,6 @@ int clz_32(int a) {
 // RV32XTHEADBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[NOT]], i1 false)
 // RV32XTHEADBB-NEXT:    ret i32 [[TMP1]]
 //
-int clo_32(int a) {
+unsigned int clo_32(unsigned int a) {
   return __builtin_riscv_clz_32(~a);
 }

diff  --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
index b4610be2714e77..6e7ecf0300fba5 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -22,7 +22,7 @@ unsigned int orc_b_32(unsigned int a) {
 // RV32ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
 // RV32ZBB-NEXT:    ret i32 [[TMP1]]
 //
-int clz_32(unsigned int a) {
+unsigned int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -34,6 +34,6 @@ int clz_32(unsigned int a) {
 // RV32ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
 // RV32ZBB-NEXT:    ret i32 [[TMP1]]
 //
-int ctz_32(unsigned int a) {
+unsigned int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }

diff  --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
index 44220627b36cf2..da74ca92137c11 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
@@ -10,7 +10,7 @@
 // RV64XTHEADBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
 // RV64XTHEADBB-NEXT:    ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+unsigned int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -23,7 +23,7 @@ int clz_32(int a) {
 // RV64XTHEADBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[NOT]], i1 false)
 // RV64XTHEADBB-NEXT:    ret i32 [[TMP1]]
 //
-int clo_32(int a) {
+unsigned int clo_32(unsigned int a) {
   return __builtin_riscv_clz_32(~a);
 }
 
@@ -36,7 +36,7 @@ int clo_32(int a) {
 // RV64XTHEADBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
 // RV64XTHEADBB-NEXT:    ret i32 [[CAST]]
 //
-int clz_64(long a) {
+unsigned int clz_64(unsigned long a) {
   return __builtin_riscv_clz_64(a);
 }
 
@@ -50,6 +50,6 @@ int clz_64(long a) {
 // RV64XTHEADBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
 // RV64XTHEADBB-NEXT:    ret i32 [[CAST]]
 //
-int clo_64(long a) {
+unsigned int clo_64(unsigned long a) {
   return __builtin_riscv_clz_64(~a);
 }

diff  --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
index 3ca77235c2b3e9..2309adfff84408 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -34,7 +34,7 @@ unsigned long orc_b_64(unsigned long a) {
 // RV64ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:    ret i32 [[TMP1]]
 //
-int clz_32(unsigned int a) {
+unsigned int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -47,7 +47,7 @@ int clz_32(unsigned int a) {
 // RV64ZBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
 // RV64ZBB-NEXT:    ret i32 [[CAST]]
 //
-int clz_64(unsigned long a) {
+unsigned int clz_64(unsigned long a) {
   return __builtin_riscv_clz_64(a);
 }
 
@@ -59,7 +59,7 @@ int clz_64(unsigned long a) {
 // RV64ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:    ret i32 [[TMP1]]
 //
-int ctz_32(unsigned int a) {
+unsigned int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
 
@@ -72,6 +72,6 @@ int ctz_32(unsigned int a) {
 // RV64ZBB-NEXT:    [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
 // RV64ZBB-NEXT:    ret i32 [[CAST]]
 //
-int ctz_64(unsigned long a) {
+unsigned int ctz_64(unsigned long a) {
   return __builtin_riscv_ctz_64(a);
 }