[clang] 2c38d63 - [8/8][RISCV] Add rounding mode control variant for vfredosum, vfredusum, vfwredosum, vfwredusum
via cfe-commits
cfe-commits at lists.llvm.org
Thu Jul 13 00:55:17 PDT 2023
Author: eopXD
Date: 2023-07-13T00:55:10-07:00
New Revision: 2c38d6332345eddb7ed0509052383dc12faef767
URL: https://github.com/llvm/llvm-project/commit/2c38d6332345eddb7ed0509052383dc12faef767
DIFF: https://github.com/llvm/llvm-project/commit/2c38d6332345eddb7ed0509052383dc12faef767.diff
LOG: [8/8][RISCV] Add rounding mode control variant for vfredosum, vfredusum, vfwredosum, vfwredusum
Depends on D154635
For the cover letter of the patch-set, please checkout D154628.
This is the 8th patch of the patch-set.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D154636
Added:
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfredosum-out-of-range.c
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfredusum-out-of-range.c
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwredosum-out-of-range.c
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwredusum-out-of-range.c
Modified:
clang/include/clang/Basic/riscv_vector.td
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index bba2f20d06b965..3aa69b124a97a2 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -371,10 +371,18 @@ let HasMaskedOffOperand = true in {
defm "" : RVVOutOp0BuiltinSet<NAME, "xfd",
[["vs", "vSv", "SvvSv"]]>;
}
+ multiclass RVVFloatingReductionBuiltinRoundingMode {
+ defm "" : RVVOutOp0BuiltinSet<NAME, "xfd",
+ [["vs", "vSv", "SvvSvu"]]>;
+ }
multiclass RVVFloatingWidenReductionBuiltin {
defm "" : RVVOutOp0BuiltinSet<NAME, "xf",
[["vs", "vSw", "SwvSw"]]>;
}
+ multiclass RVVFloatingWidenReductionBuiltinRoundingMode {
+ defm "" : RVVOutOp0BuiltinSet<NAME, "xf",
+ [["vs", "vSw", "SwvSwu"]]>;
+ }
}
multiclass RVVIntReductionBuiltinSet
@@ -2469,12 +2477,65 @@ let HasMaskedOffOperand = true in {
// 15.3. Vector Single-Width Floating-Point Reduction Instructions
defm vfredmax : RVVFloatingReductionBuiltin;
defm vfredmin : RVVFloatingReductionBuiltin;
-defm vfredusum : RVVFloatingReductionBuiltin;
-defm vfredosum : RVVFloatingReductionBuiltin;
+let ManualCodegen = [{
+ {
+ // LLVM intrinsic
+ // Unmasked: (passthru, op0, op1, round_mode, vl)
+ // Masked: (passthru, vector_in, vector_in/scalar_in, mask, frm, vl, policy)
+
+ SmallVector<llvm::Value*, 7> Operands;
+ bool HasMaskedOff = !(
+ (IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
+ (!IsMasked && PolicyAttrs & RVV_VTA));
+ bool HasRoundModeOp = IsMasked ?
+ (HasMaskedOff ? Ops.size() == 6 : Ops.size() == 5) :
+ (HasMaskedOff ? Ops.size() == 5 : Ops.size() == 4);
+
+ unsigned Offset = IsMasked ?
+ (HasMaskedOff ? 2 : 1) : (HasMaskedOff ? 1 : 0);
+
+ if (!HasMaskedOff)
+ Operands.push_back(llvm::PoisonValue::get(ResultType));
+ else
+ Operands.push_back(Ops[IsMasked ? 1 : 0]);
-// 15.4. Vector Widening Floating-Point Reduction Instructions
-defm vfwredusum : RVVFloatingWidenReductionBuiltin;
-defm vfwredosum : RVVFloatingWidenReductionBuiltin;
+ Operands.push_back(Ops[Offset]); // op0
+ Operands.push_back(Ops[Offset + 1]); // op1
+
+ if (IsMasked)
+ Operands.push_back(Ops[0]); // mask
+
+ if (HasRoundModeOp) {
+ Operands.push_back(Ops[Offset + 2]); // frm
+ Operands.push_back(Ops[Offset + 3]); // vl
+ } else {
+ Operands.push_back(ConstantInt::get(Ops[Offset + 2]->getType(), 7)); // frm
+ Operands.push_back(Ops[Offset + 2]); // vl
+ }
+
+ IntrinsicTypes = {ResultType, Ops[Offset]->getType(),
+ Ops.back()->getType()};
+ llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
+ return Builder.CreateCall(F, Operands, "");
+ }
+}] in {
+ let HasFRMRoundModeOp = 1 in {
+ // 15.3. Vector Single-Width Floating-Point Reduction Instructions
+ defm vfredusum : RVVFloatingReductionBuiltinRoundingMode;
+ defm vfredosum : RVVFloatingReductionBuiltinRoundingMode;
+
+ // 15.4. Vector Widening Floating-Point Reduction Instructions
+ defm vfwredusum : RVVFloatingWidenReductionBuiltinRoundingMode;
+ defm vfwredosum : RVVFloatingWidenReductionBuiltinRoundingMode;
+ }
+ // 15.3. Vector Single-Width Floating-Point Reduction Instructions
+ defm vfredusum : RVVFloatingReductionBuiltin;
+ defm vfredosum : RVVFloatingReductionBuiltin;
+
+ // 15.4. Vector Widening Floating-Point Reduction Instructions
+ defm vfwredusum : RVVFloatingWidenReductionBuiltin;
+ defm vfwredosum : RVVFloatingWidenReductionBuiltin;
+}
}
// 16. Vector Mask Instructions
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 693ff523f822df..d0680b13c294c5 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -4842,6 +4842,10 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm:
case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm:
case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm:
+ case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm:
+ case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm:
+ case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm:
+ case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm:
case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tu:
case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tu:
case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tu:
@@ -4889,6 +4893,10 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tu:
case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tu:
+ case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tu:
+ case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tu:
+ case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tu:
+ case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tu:
case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm:
case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm:
case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm:
@@ -4957,6 +4965,10 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tama:
+ case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tama:
+ case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tama:
+ case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tama:
+ case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tama:
case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tum:
case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tum:
case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tum:
@@ -5065,6 +5077,10 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tum:
+ case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tum:
+ case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tum:
+ case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tum:
+ case RISCVVector::BI__builtin_rvv_vfwredusum_vs_rm_tum:
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tumu:
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
index e419aa49ca5db5..75f5db44d17150 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1(vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1(vfloat16mf4_t vector, vfloat16m1_t s
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1(vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1(vfloat16mf2_t vector, vfloat16m1_t s
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m1_f16m1(vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat16m1_t test_vfredosum_vs_f16m1_f16m1(vfloat16m1_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m2_f16m1(vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat16m1_t test_vfredosum_vs_f16m2_f16m1(vfloat16m2_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m4_f16m1(vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat16m1_t test_vfredosum_vs_f16m4_f16m1(vfloat16m4_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m8_f16m1(vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat16m1_t test_vfredosum_vs_f16m8_f16m1(vfloat16m8_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1(vfloat32mf2_t vector, vfloat32m1_t s
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m1_f32m1(vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat32m1_t test_vfredosum_vs_f32m1_f32m1(vfloat32m1_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m2_f32m1(vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat32m1_t test_vfredosum_vs_f32m2_f32m1(vfloat32m2_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m4_f32m1(vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat32m1_t test_vfredosum_vs_f32m4_f32m1(vfloat32m4_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m8_f32m1(vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat32m1_t test_vfredosum_vs_f32m8_f32m1(vfloat32m8_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m1_f64m1(vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat64m1_t test_vfredosum_vs_f64m1_f64m1(vfloat64m1_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m2_f64m1(vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat64m1_t test_vfredosum_vs_f64m2_f64m1(vfloat64m2_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m4_f64m1(vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat64m1_t test_vfredosum_vs_f64m4_f64m1(vfloat64m4_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m8_f64m1(vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat64m1_t test_vfredosum_vs_f64m8_f64m1(vfloat64m8_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_m(vbool64_t mask, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_m(vbool64_t mask, vfloat16mf4_t vect
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_m(vbool32_t mask, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_m(vbool32_t mask, vfloat16mf2_t vect
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_m(vbool16_t mask, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_m(vbool16_t mask, vfloat16m1_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_m(vbool8_t mask, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_m(vbool8_t mask, vfloat16m2_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_m(vbool4_t mask, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_m(vbool4_t mask, vfloat16m4_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_m(vbool2_t mask, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -220,7 +220,7 @@ vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_m(vbool2_t mask, vfloat16m8_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_m(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -230,7 +230,7 @@ vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_m(vbool64_t mask, vfloat32mf2_t vect
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_m(vbool32_t mask, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -240,7 +240,7 @@ vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_m(vbool32_t mask, vfloat32m1_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_m(vbool16_t mask, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -250,7 +250,7 @@ vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_m(vbool16_t mask, vfloat32m2_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_m(vbool8_t mask, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -260,7 +260,7 @@ vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_m(vbool8_t mask, vfloat32m4_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_m(vbool4_t mask, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -270,7 +270,7 @@ vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_m(vbool4_t mask, vfloat32m8_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_m(vbool64_t mask, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -280,7 +280,7 @@ vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_m(vbool64_t mask, vfloat64m1_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_m(vbool32_t mask, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -290,7 +290,7 @@ vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_m(vbool32_t mask, vfloat64m2_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_m(vbool16_t mask, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -300,10 +300,310 @@ vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_m(vbool16_t mask, vfloat64m4_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_m(vbool8_t mask, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfredosum_vs_f64m8_f64m1_m(mask, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_rm(vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16mf4_f16m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_rm(vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16mf2_f16m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_rm(vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m1_f16m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_rm(vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m2_f16m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_rm(vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m4_f16m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_rm(vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m8_f16m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_rm(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32mf2_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_rm(vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m1_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_rm(vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m2_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_rm(vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m4_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_rm(vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m8_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_rm(vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m1_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_rm(vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m2_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_rm(vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m4_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_rm(vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m8_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_rm_m(vbool64_t mask, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16mf4_f16m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_rm_m(vbool32_t mask, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16mf2_f16m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m1_f16m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_rm_m(vbool8_t mask, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m2_f16m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_rm_m(vbool4_t mask, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m4_f16m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_rm_m(vbool2_t mask, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m8_f16m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_rm_m(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32mf2_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m1_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_rm_m(vbool16_t mask, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m2_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_rm_m(vbool8_t mask, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m4_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_rm_m(vbool4_t mask, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m8_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m1_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_rm_m(vbool32_t mask, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m2_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_rm_m(vbool16_t mask, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m4_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_rm_m(vbool8_t mask, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m8_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
index 99d01f2075f1a2..33000f7c3ae6c4 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1(vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1(vfloat16mf4_t vector, vfloat16m1_t s
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1(vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1(vfloat16mf2_t vector, vfloat16m1_t s
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m1_f16m1(vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat16m1_t test_vfredusum_vs_f16m1_f16m1(vfloat16m1_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m2_f16m1(vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat16m1_t test_vfredusum_vs_f16m2_f16m1(vfloat16m2_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m4_f16m1(vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat16m1_t test_vfredusum_vs_f16m4_f16m1(vfloat16m4_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m8_f16m1(vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat16m1_t test_vfredusum_vs_f16m8_f16m1(vfloat16m8_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1(vfloat32mf2_t vector, vfloat32m1_t s
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m1_f32m1(vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat32m1_t test_vfredusum_vs_f32m1_f32m1(vfloat32m1_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m2_f32m1(vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat32m1_t test_vfredusum_vs_f32m2_f32m1(vfloat32m2_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m4_f32m1(vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat32m1_t test_vfredusum_vs_f32m4_f32m1(vfloat32m4_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m8_f32m1(vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat32m1_t test_vfredusum_vs_f32m8_f32m1(vfloat32m8_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m1_f64m1(vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat64m1_t test_vfredusum_vs_f64m1_f64m1(vfloat64m1_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m2_f64m1(vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat64m1_t test_vfredusum_vs_f64m2_f64m1(vfloat64m2_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m4_f64m1(vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat64m1_t test_vfredusum_vs_f64m4_f64m1(vfloat64m4_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m8_f64m1(vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat64m1_t test_vfredusum_vs_f64m8_f64m1(vfloat64m8_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_m(vbool64_t mask, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_m(vbool64_t mask, vfloat16mf4_t vect
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_m(vbool32_t mask, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_m(vbool32_t mask, vfloat16mf2_t vect
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_m(vbool16_t mask, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_m(vbool16_t mask, vfloat16m1_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_m(vbool8_t mask, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_m(vbool8_t mask, vfloat16m2_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_m(vbool4_t mask, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_m(vbool4_t mask, vfloat16m4_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_m(vbool2_t mask, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -220,7 +220,7 @@ vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_m(vbool2_t mask, vfloat16m8_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_m(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -230,7 +230,7 @@ vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_m(vbool64_t mask, vfloat32mf2_t vect
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_m(vbool32_t mask, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -240,7 +240,7 @@ vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_m(vbool32_t mask, vfloat32m1_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_m(vbool16_t mask, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -250,7 +250,7 @@ vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_m(vbool16_t mask, vfloat32m2_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_m(vbool8_t mask, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -260,7 +260,7 @@ vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_m(vbool8_t mask, vfloat32m4_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_m(vbool4_t mask, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -270,7 +270,7 @@ vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_m(vbool4_t mask, vfloat32m8_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_m(vbool64_t mask, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -280,7 +280,7 @@ vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_m(vbool64_t mask, vfloat64m1_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_m(vbool32_t mask, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -290,7 +290,7 @@ vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_m(vbool32_t mask, vfloat64m2_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_m(vbool16_t mask, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -300,10 +300,310 @@ vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_m(vbool16_t mask, vfloat64m4_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_m(vbool8_t mask, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfredusum_vs_f64m8_f64m1_m(mask, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_rm(vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16mf4_f16m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_rm(vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16mf2_f16m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_rm(vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m1_f16m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_rm(vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m2_f16m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_rm(vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m4_f16m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_rm(vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m8_f16m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_rm(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32mf2_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_rm(vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m1_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_rm(vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m2_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_rm(vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m4_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_rm(vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m8_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_rm(vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m1_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_rm(vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m2_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_rm(vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m4_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_rm(vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m8_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_rm_m(vbool64_t mask, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16mf4_f16m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_rm_m(vbool32_t mask, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16mf2_f16m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m1_f16m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_rm_m(vbool8_t mask, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m2_f16m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_rm_m(vbool4_t mask, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m4_f16m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_rm_m(vbool2_t mask, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m8_f16m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_rm_m(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32mf2_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m1_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_rm_m(vbool16_t mask, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m2_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_rm_m(vbool8_t mask, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m4_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_rm_m(vbool4_t mask, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m8_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m1_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_rm_m(vbool32_t mask, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m2_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_rm_m(vbool16_t mask, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m4_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_rm_m(vbool8_t mask, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m8_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
index fe604470893051..364319f44dafe8 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1(vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1(vfloat16mf4_t vector, vfloat32m1_t
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1(vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1(vfloat16mf2_t vector, vfloat32m1_t
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1(vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1(vfloat16m1_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1(vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1(vfloat16m2_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1(vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1(vfloat16m4_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1(vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1(vfloat16m8_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1(vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1(vfloat32mf2_t vector, vfloat64m1_t
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1(vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1(vfloat32m1_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1(vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1(vfloat32m2_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1(vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1(vfloat32m4_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1(vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1(vfloat32m8_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_m(vbool64_t mask, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_m(vbool64_t mask, vfloat16mf4_t vec
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_m(vbool32_t mask, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_m(vbool32_t mask, vfloat16mf2_t vec
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_m(vbool16_t mask, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_m(vbool16_t mask, vfloat16m1_t vecto
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_m(vbool8_t mask, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_m(vbool8_t mask, vfloat16m2_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_m(vbool4_t mask, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_m(vbool4_t mask, vfloat16m4_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_m(vbool2_t mask, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_m(vbool2_t mask, vfloat16m8_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat32mf2_t vec
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat32m1_t vecto
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat32m2_t vecto
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -220,10 +220,230 @@ vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat32m4_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_m(vbool4_t mask, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfwredosum_vs_f32m8_f64m1_m(mask, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_rm(vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16mf4_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_rm(vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16mf2_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_rm(vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m1_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_rm(vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m2_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_rm(vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m4_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_rm(vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m8_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_rm(vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32mf2_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_rm(vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m1_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_rm(vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m2_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_rm(vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m4_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_rm(vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m8_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_rm_m(vbool64_t mask, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16mf4_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_rm_m(vbool32_t mask, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16mf2_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_rm_m(vbool16_t mask, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m1_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_rm_m(vbool8_t mask, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m2_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_rm_m(vbool4_t mask, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m4_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_rm_m(vbool2_t mask, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m8_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_rm_m(vbool64_t mask, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32mf2_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_rm_m(vbool32_t mask, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m1_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_rm_m(vbool16_t mask, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m2_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_rm_m(vbool8_t mask, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m4_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_rm_m(vbool4_t mask, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m8_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
index e751e0ba0dca90..501411ef51fcd4 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1(vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1(vfloat16mf4_t vector, vfloat32m1_t
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1(vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1(vfloat16mf2_t vector, vfloat32m1_t
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1(vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1(vfloat16m1_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1(vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1(vfloat16m2_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1(vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1(vfloat16m4_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1(vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1(vfloat16m8_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1(vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1(vfloat32mf2_t vector, vfloat64m1_t
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1(vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1(vfloat32m1_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1(vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1(vfloat32m2_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1(vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1(vfloat32m4_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1(vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1(vfloat32m8_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_m(vbool64_t mask, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_m(vbool64_t mask, vfloat16mf4_t vec
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_m(vbool32_t mask, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_m(vbool32_t mask, vfloat16mf2_t vec
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_m(vbool16_t mask, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_m(vbool16_t mask, vfloat16m1_t vecto
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_m(vbool8_t mask, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_m(vbool8_t mask, vfloat16m2_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_m(vbool4_t mask, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_m(vbool4_t mask, vfloat16m4_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_m(vbool2_t mask, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_m(vbool2_t mask, vfloat16m8_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat32mf2_t vec
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat32m1_t vecto
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat32m2_t vecto
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -220,10 +220,230 @@ vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat32m4_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_m(vbool4_t mask, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfwredusum_vs_f32m8_f64m1_m(mask, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_rm(vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16mf4_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_rm(vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16mf2_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_rm(vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m1_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_rm(vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m2_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_rm(vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m4_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_rm(vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m8_f32m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_rm(vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32mf2_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_rm(vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m1_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_rm(vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m2_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_rm(vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m4_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_rm(vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m8_f64m1_rm(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_rm_m(vbool64_t mask, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16mf4_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_rm_m(vbool32_t mask, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16mf2_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_rm_m(vbool16_t mask, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m1_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_rm_m(vbool8_t mask, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m2_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_rm_m(vbool4_t mask, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m4_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_rm_m(vbool2_t mask, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m8_f32m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_rm_m(vbool64_t mask, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32mf2_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_rm_m(vbool32_t mask, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m1_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_rm_m(vbool16_t mask, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m2_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_rm_m(vbool8_t mask, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m4_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_rm_m(vbool4_t mask, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m8_f64m1_rm_m(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
index 4eb54775f2fb0f..66888f1b0b849f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1(vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1(vfloat16mf4_t vector, vfloat16m1_t s
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1(vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1(vfloat16mf2_t vector, vfloat16m1_t s
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m1_f16m1(vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat16m1_t test_vfredosum_vs_f16m1_f16m1(vfloat16m1_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m2_f16m1(vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat16m1_t test_vfredosum_vs_f16m2_f16m1(vfloat16m2_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m4_f16m1(vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat16m1_t test_vfredosum_vs_f16m4_f16m1(vfloat16m4_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m8_f16m1(vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat16m1_t test_vfredosum_vs_f16m8_f16m1(vfloat16m8_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1(vfloat32mf2_t vector, vfloat32m1_t s
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m1_f32m1(vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat32m1_t test_vfredosum_vs_f32m1_f32m1(vfloat32m1_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m2_f32m1(vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat32m1_t test_vfredosum_vs_f32m2_f32m1(vfloat32m2_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m4_f32m1(vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat32m1_t test_vfredosum_vs_f32m4_f32m1(vfloat32m4_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m8_f32m1(vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat32m1_t test_vfredosum_vs_f32m8_f32m1(vfloat32m8_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m1_f64m1(vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat64m1_t test_vfredosum_vs_f64m1_f64m1(vfloat64m1_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m2_f64m1(vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat64m1_t test_vfredosum_vs_f64m2_f64m1(vfloat64m2_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m4_f64m1(vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat64m1_t test_vfredosum_vs_f64m4_f64m1(vfloat64m4_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m8_f64m1(vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat64m1_t test_vfredosum_vs_f64m8_f64m1(vfloat64m8_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_m(vbool64_t mask, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_m(vbool64_t mask, vfloat16mf4_t vect
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_m(vbool32_t mask, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_m(vbool32_t mask, vfloat16mf2_t vect
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_m(vbool16_t mask, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_m(vbool16_t mask, vfloat16m1_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_m(vbool8_t mask, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_m(vbool8_t mask, vfloat16m2_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_m(vbool4_t mask, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_m(vbool4_t mask, vfloat16m4_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_m(vbool2_t mask, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -220,7 +220,7 @@ vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_m(vbool2_t mask, vfloat16m8_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_m(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -230,7 +230,7 @@ vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_m(vbool64_t mask, vfloat32mf2_t vect
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_m(vbool32_t mask, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -240,7 +240,7 @@ vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_m(vbool32_t mask, vfloat32m1_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_m(vbool16_t mask, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -250,7 +250,7 @@ vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_m(vbool16_t mask, vfloat32m2_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_m(vbool8_t mask, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -260,7 +260,7 @@ vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_m(vbool8_t mask, vfloat32m4_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_m(vbool4_t mask, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -270,7 +270,7 @@ vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_m(vbool4_t mask, vfloat32m8_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_m(vbool64_t mask, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -280,7 +280,7 @@ vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_m(vbool64_t mask, vfloat64m1_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_m(vbool32_t mask, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -290,7 +290,7 @@ vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_m(vbool32_t mask, vfloat64m2_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_m(vbool16_t mask, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -300,10 +300,310 @@ vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_m(vbool16_t mask, vfloat64m4_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_m(vbool8_t mask, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfredosum(mask, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_rm(vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_rm(vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_rm(vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_rm(vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_rm(vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_rm(vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_rm(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_rm(vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_rm(vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_rm(vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_rm(vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_rm(vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_rm(vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_rm(vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_rm(vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_rm_m(vbool64_t mask, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_rm_m(vbool32_t mask, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_rm_m(vbool8_t mask, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_rm_m(vbool4_t mask, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_rm_m(vbool2_t mask, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_rm_m(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_rm_m(vbool16_t mask, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_rm_m(vbool8_t mask, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_rm_m(vbool4_t mask, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_rm_m(vbool32_t mask, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_rm_m(vbool16_t mask, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_rm_m(vbool8_t mask, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
index 82ae943d90729b..77ff64bbfe94ba 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1(vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1(vfloat16mf4_t vector, vfloat16m1_t s
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1(vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1(vfloat16mf2_t vector, vfloat16m1_t s
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m1_f16m1(vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat16m1_t test_vfredusum_vs_f16m1_f16m1(vfloat16m1_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m2_f16m1(vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat16m1_t test_vfredusum_vs_f16m2_f16m1(vfloat16m2_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m4_f16m1(vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat16m1_t test_vfredusum_vs_f16m4_f16m1(vfloat16m4_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m8_f16m1(vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat16m1_t test_vfredusum_vs_f16m8_f16m1(vfloat16m8_t vector, vfloat16m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1(vfloat32mf2_t vector, vfloat32m1_t s
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m1_f32m1(vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat32m1_t test_vfredusum_vs_f32m1_f32m1(vfloat32m1_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m2_f32m1(vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat32m1_t test_vfredusum_vs_f32m2_f32m1(vfloat32m2_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m4_f32m1(vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat32m1_t test_vfredusum_vs_f32m4_f32m1(vfloat32m4_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m8_f32m1(vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat32m1_t test_vfredusum_vs_f32m8_f32m1(vfloat32m8_t vector, vfloat32m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m1_f64m1(vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat64m1_t test_vfredusum_vs_f64m1_f64m1(vfloat64m1_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m2_f64m1(vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat64m1_t test_vfredusum_vs_f64m2_f64m1(vfloat64m2_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m4_f64m1(vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat64m1_t test_vfredusum_vs_f64m4_f64m1(vfloat64m4_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m8_f64m1(vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat64m1_t test_vfredusum_vs_f64m8_f64m1(vfloat64m8_t vector, vfloat64m1_t sca
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_m(vbool64_t mask, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_m(vbool64_t mask, vfloat16mf4_t vect
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_m(vbool32_t mask, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_m(vbool32_t mask, vfloat16mf2_t vect
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_m(vbool16_t mask, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_m(vbool16_t mask, vfloat16m1_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_m(vbool8_t mask, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_m(vbool8_t mask, vfloat16m2_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_m(vbool4_t mask, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_m(vbool4_t mask, vfloat16m4_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_m(vbool2_t mask, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -220,7 +220,7 @@ vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_m(vbool2_t mask, vfloat16m8_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_m(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -230,7 +230,7 @@ vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_m(vbool64_t mask, vfloat32mf2_t vect
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_m(vbool32_t mask, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -240,7 +240,7 @@ vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_m(vbool32_t mask, vfloat32m1_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_m(vbool16_t mask, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -250,7 +250,7 @@ vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_m(vbool16_t mask, vfloat32m2_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_m(vbool8_t mask, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -260,7 +260,7 @@ vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_m(vbool8_t mask, vfloat32m4_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_m(vbool4_t mask, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -270,7 +270,7 @@ vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_m(vbool4_t mask, vfloat32m8_t vector,
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_m(vbool64_t mask, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -280,7 +280,7 @@ vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_m(vbool64_t mask, vfloat64m1_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_m(vbool32_t mask, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -290,7 +290,7 @@ vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_m(vbool32_t mask, vfloat64m2_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_m(vbool16_t mask, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -300,10 +300,310 @@ vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_m(vbool16_t mask, vfloat64m4_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_m(vbool8_t mask, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfredusum(mask, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_rm(vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_rm(vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_rm(vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_rm(vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_rm(vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_rm
+// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_rm(vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_rm(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_rm(vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_rm(vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_rm(vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_rm(vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_rm(vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_rm(vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_rm(vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_rm(vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_rm_m(vbool64_t mask, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_rm_m(vbool32_t mask, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_rm_m(vbool8_t mask, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_rm_m(vbool4_t mask, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_rm_m(vbool2_t mask, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_rm_m(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_rm_m(vbool16_t mask, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_rm_m(vbool8_t mask, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_rm_m(vbool4_t mask, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_rm_m(vbool32_t mask, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> poison, <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_rm_m(vbool16_t mask, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> poison, <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_rm_m(vbool8_t mask, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
index 1a519d057fefbe..055175633f0d91 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1(vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1(vfloat16mf4_t vector, vfloat32m1_t
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1(vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1(vfloat16mf2_t vector, vfloat32m1_t
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1(vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1(vfloat16m1_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1(vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1(vfloat16m2_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1(vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1(vfloat16m4_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1(vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1(vfloat16m8_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1(vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1(vfloat32mf2_t vector, vfloat64m1_t
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1(vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1(vfloat32m1_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1(vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1(vfloat32m2_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1(vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1(vfloat32m4_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1(vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1(vfloat32m8_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_m(vbool64_t mask, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_m(vbool64_t mask, vfloat16mf4_t vec
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_m(vbool32_t mask, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_m(vbool32_t mask, vfloat16mf2_t vec
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_m(vbool16_t mask, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_m(vbool16_t mask, vfloat16m1_t vecto
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_m(vbool8_t mask, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_m(vbool8_t mask, vfloat16m2_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_m(vbool4_t mask, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_m(vbool4_t mask, vfloat16m4_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_m(vbool2_t mask, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_m(vbool2_t mask, vfloat16m8_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat32mf2_t vec
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat32m1_t vecto
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat32m2_t vecto
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -220,10 +220,230 @@ vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat32m4_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_m(vbool4_t mask, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfwredosum(mask, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_rm(vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_rm(vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_rm(vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_rm(vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_rm(vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_rm(vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_rm(vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_rm(vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_rm(vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_rm(vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_rm(vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_rm_m(vbool64_t mask, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_rm_m(vbool32_t mask, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_rm_m(vbool16_t mask, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_rm_m(vbool8_t mask, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_rm_m(vbool4_t mask, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_rm_m(vbool2_t mask, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_rm_m(vbool64_t mask, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_rm_m(vbool32_t mask, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_rm_m(vbool16_t mask, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_rm_m(vbool8_t mask, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_rm_m(vbool4_t mask, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
index e83b687a49047a..fbd20e3d2bf8eb 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1(vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1(vfloat16mf4_t vector, vfloat32m1_t
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1(vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1(vfloat16mf2_t vector, vfloat32m1_t
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1(vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1(vfloat16m1_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1(vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1(vfloat16m2_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1(vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1(vfloat16m4_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1(vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1(vfloat16m8_t vector, vfloat32m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1(vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1(vfloat32mf2_t vector, vfloat64m1_t
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1(vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1(vfloat32m1_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1(vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1(vfloat32m2_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1(vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1(vfloat32m4_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1(vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1(vfloat32m8_t vector, vfloat64m1_t sc
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_m(vbool64_t mask, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_m(vbool64_t mask, vfloat16mf4_t vec
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_m(vbool32_t mask, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_m(vbool32_t mask, vfloat16mf2_t vec
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_m(vbool16_t mask, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_m(vbool16_t mask, vfloat16m1_t vecto
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_m(vbool8_t mask, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_m(vbool8_t mask, vfloat16m2_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_m(vbool4_t mask, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_m(vbool4_t mask, vfloat16m4_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_m(vbool2_t mask, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_m(vbool2_t mask, vfloat16m8_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat32mf2_t vec
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat32m1_t vecto
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat32m2_t vecto
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -220,10 +220,230 @@ vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat32m4_t vector
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_m(vbool4_t mask, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfwredusum(mask, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_rm(vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_rm(vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_rm(vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_rm(vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_rm(vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_rm
+// CHECK-RV64-SAME: (<vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_rm(vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_rm(vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_rm(vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_rm(vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_rm(vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1_rm
+// CHECK-RV64-SAME: (<vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_rm(vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_rm_m(vbool64_t mask, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_rm_m(vbool32_t mask, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_rm_m(vbool16_t mask, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_rm_m(vbool8_t mask, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_rm_m(vbool4_t mask, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_rm_m(vbool2_t mask, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_rm_m(vbool64_t mask, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_rm_m(vbool32_t mask, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_rm_m(vbool16_t mask, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> poison, <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_rm_m(vbool8_t mask, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1_rm_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> poison, <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_rm_m(vbool4_t mask, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum(mask, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
index 658af50af22f9c..964c4f61011eae 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m1
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m2
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m4
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m8
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m1
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m2
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m4
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m8
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m1
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m2
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m4
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m8
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_tum(vbool64_t mask, vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_tum(vbool64_t mask, vfloat16m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_tum(vbool32_t mask, vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_tum(vbool32_t mask, vfloat16m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_tum(vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_tum(vbool16_t mask, vfloat16m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_tum(vbool8_t mask, vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_tum(vbool8_t mask, vfloat16m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_tum(vbool4_t mask, vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_tum(vbool4_t mask, vfloat16m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_tum(vbool2_t mask, vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -220,7 +220,7 @@ vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_tum(vbool2_t mask, vfloat16m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -230,7 +230,7 @@ vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -240,7 +240,7 @@ vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_tum(vbool32_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -250,7 +250,7 @@ vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_tum(vbool16_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -260,7 +260,7 @@ vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_tum(vbool8_t mask, vfloat32m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -270,7 +270,7 @@ vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_tum(vbool4_t mask, vfloat32m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -280,7 +280,7 @@ vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_tum(vbool64_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -290,7 +290,7 @@ vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_tum(vbool32_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -300,10 +300,310 @@ vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_tum(vbool16_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfredosum_vs_f64m8_f64m1_tum(mask, maskedoff, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16mf4_f16m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16mf2_f16m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m1_f16m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m2_f16m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m4_f16m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m8_f16m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32mf2_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m1_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m2_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m4_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m8_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m1_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m2_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m4_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m8_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_rm_tum(vbool64_t mask, vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16mf4_f16m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_rm_tum(vbool32_t mask, vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16mf2_f16m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m1_f16m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_rm_tum(vbool8_t mask, vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m2_f16m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_rm_tum(vbool4_t mask, vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m4_f16m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_rm_tum(vbool2_t mask, vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f16m8_f16m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_rm_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32mf2_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m1_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_rm_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m2_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_rm_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m4_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_rm_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f32m8_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m1_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_rm_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m2_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_rm_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m4_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_rm_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_vs_f64m8_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
index e8755058d52095..b3c6b5e0902d15 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m1
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m2
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m4
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m8
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m1
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m2
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m4
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m8
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m1
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m2
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m4
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m8
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_tum(vbool64_t mask, vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_tum(vbool64_t mask, vfloat16m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_tum(vbool32_t mask, vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_tum(vbool32_t mask, vfloat16m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_tum(vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_tum(vbool16_t mask, vfloat16m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_tum(vbool8_t mask, vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_tum(vbool8_t mask, vfloat16m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_tum(vbool4_t mask, vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_tum(vbool4_t mask, vfloat16m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_tum(vbool2_t mask, vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -220,7 +220,7 @@ vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_tum(vbool2_t mask, vfloat16m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -230,7 +230,7 @@ vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -240,7 +240,7 @@ vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_tum(vbool32_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -250,7 +250,7 @@ vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_tum(vbool16_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -260,7 +260,7 @@ vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_tum(vbool8_t mask, vfloat32m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -270,7 +270,7 @@ vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_tum(vbool4_t mask, vfloat32m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -280,7 +280,7 @@ vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_tum(vbool64_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -290,7 +290,7 @@ vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_tum(vbool32_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -300,10 +300,310 @@ vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_tum(vbool16_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfredusum_vs_f64m8_f64m1_tum(mask, maskedoff, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16mf4_f16m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16mf2_f16m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m1_f16m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m2_f16m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m4_f16m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m8_f16m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32mf2_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m1_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m2_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m4_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m8_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m1_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m2_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m4_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m8_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_rm_tum(vbool64_t mask, vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16mf4_f16m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_rm_tum(vbool32_t mask, vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16mf2_f16m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m1_f16m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_rm_tum(vbool8_t mask, vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m2_f16m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_rm_tum(vbool4_t mask, vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m4_f16m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_rm_tum(vbool2_t mask, vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f16m8_f16m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_rm_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32mf2_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m1_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_rm_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m2_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_rm_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m4_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_rm_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f32m8_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m1_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_rm_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m2_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_rm_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m4_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_rm_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_vs_f64m8_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
index 4347cf070bd505..90c06b09b7c4fe 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_tum(vbool64_t mask, vfloat32m1_t ma
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_tum(vbool32_t mask, vfloat32m1_t ma
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_tum(vbool16_t mask, vfloat32m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_tum(vbool8_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_tum(vbool4_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_tum(vbool2_t mask, vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_tum(vbool2_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_tum(vbool64_t mask, vfloat64m1_t ma
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_tum(vbool32_t mask, vfloat64m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_tum(vbool16_t mask, vfloat64m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -220,10 +220,230 @@ vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_tum(vbool8_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_tum(vbool4_t mask, vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfwredosum_vs_f32m8_f64m1_tum(mask, maskedoff, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16mf4_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16mf2_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m1_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m2_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m4_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m8_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32mf2_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m1_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m2_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m4_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m8_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_rm_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16mf4_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16mf2_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_rm_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m1_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_rm_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m2_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_rm_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m4_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_rm_tum(vbool2_t mask, vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f16m8_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32mf2_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_rm_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m1_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_rm_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m2_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_rm_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m4_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_rm_tum(vbool4_t mask, vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m8_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
index b6f5434b9ea63a..920bf9558e87b3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_tum(vbool64_t mask, vfloat32m1_t ma
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_tum(vbool32_t mask, vfloat32m1_t ma
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_tum(vbool16_t mask, vfloat32m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_tum(vbool8_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_tum(vbool4_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_tum(vbool2_t mask, vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_tum(vbool2_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_tum(vbool64_t mask, vfloat64m1_t ma
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_tum(vbool32_t mask, vfloat64m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_tum(vbool16_t mask, vfloat64m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -220,10 +220,230 @@ vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_tum(vbool8_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_tum(vbool4_t mask, vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfwredusum_vs_f32m8_f64m1_tum(mask, maskedoff, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16mf4_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16mf2_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m1_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m2_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m4_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m8_f32m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32mf2_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m1_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m2_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m4_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m8_f64m1_rm_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_rm_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16mf4_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16mf2_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_rm_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m1_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_rm_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m2_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_rm_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m4_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_rm_tum(vbool2_t mask, vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f16m8_f32m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32mf2_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_rm_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m1_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_rm_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m2_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_rm_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m4_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_rm_tum(vbool4_t mask, vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m8_f64m1_rm_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
index c0d2a1448ab2ac..d2ea8d1d5be6ee 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m1
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m2
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m4
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m8
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m1
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m2
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m4
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m8
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m1
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m2
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m4
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m8
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_tum(vbool64_t mask, vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_tum(vbool64_t mask, vfloat16m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_tum(vbool32_t mask, vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_tum(vbool32_t mask, vfloat16m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_tum(vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_tum(vbool16_t mask, vfloat16m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_tum(vbool8_t mask, vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_tum(vbool8_t mask, vfloat16m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_tum(vbool4_t mask, vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_tum(vbool4_t mask, vfloat16m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_tum(vbool2_t mask, vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -220,7 +220,7 @@ vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_tum(vbool2_t mask, vfloat16m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -230,7 +230,7 @@ vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -240,7 +240,7 @@ vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_tum(vbool32_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -250,7 +250,7 @@ vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_tum(vbool16_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -260,7 +260,7 @@ vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_tum(vbool8_t mask, vfloat32m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -270,7 +270,7 @@ vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_tum(vbool4_t mask, vfloat32m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -280,7 +280,7 @@ vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_tum(vbool64_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -290,7 +290,7 @@ vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_tum(vbool32_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -300,10 +300,310 @@ vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_tum(vbool16_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1_rm_tum(vbool64_t mask, vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1_rm_tum(vbool32_t mask, vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m1_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m2_f16m1_rm_tum(vbool8_t mask, vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m4_f16m1_rm_tum(vbool4_t mask, vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_rm_tum(vbool2_t mask, vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_rm_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m2_f32m1_rm_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m4_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m4_f32m1_rm_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m8_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredosum_vs_f32m8_f32m1_rm_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m1_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m1_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m2_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m2_f64m1_rm_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m4_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m4_f64m1_rm_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredosum_vs_f64m8_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_rm_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
index 7c1587f3457227..ad13105909d1ac 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m1
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m2
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m4
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_tu(vfloat16m1_t maskedoff, vfloat16m8
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m1
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m2
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m4
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat32m8
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m1
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m2
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m4
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat64m8
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_tum(vbool64_t mask, vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_tum(vbool64_t mask, vfloat16m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_tum(vbool32_t mask, vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_tum(vbool32_t mask, vfloat16m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_tum(vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_tum(vbool16_t mask, vfloat16m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_tum(vbool8_t mask, vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_tum(vbool8_t mask, vfloat16m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_tum(vbool4_t mask, vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_tum(vbool4_t mask, vfloat16m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_tum(vbool2_t mask, vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
@@ -220,7 +220,7 @@ vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_tum(vbool2_t mask, vfloat16m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -230,7 +230,7 @@ vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -240,7 +240,7 @@ vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_tum(vbool32_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -250,7 +250,7 @@ vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_tum(vbool16_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -260,7 +260,7 @@ vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_tum(vbool8_t mask, vfloat32m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -270,7 +270,7 @@ vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_tum(vbool4_t mask, vfloat32m1_t maske
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -280,7 +280,7 @@ vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_tum(vbool64_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -290,7 +290,7 @@ vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_tum(vbool32_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -300,10 +300,310 @@ vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_tum(vbool16_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_rm_tu(vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1_rm_tum(vbool64_t mask, vfloat16m1_t maskedoff, vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1_rm_tum(vbool32_t mask, vfloat16m1_t maskedoff, vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m1_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t maskedoff, vfloat16m1_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m2_f16m1_rm_tum(vbool8_t mask, vfloat16m1_t maskedoff, vfloat16m2_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m4_f16m1_rm_tum(vbool4_t mask, vfloat16m1_t maskedoff, vfloat16m4_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 4 x half> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 4 x half> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfredusum_vs_f16m8_f16m1_rm_tum(vbool2_t mask, vfloat16m1_t maskedoff, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_rm_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m2_f32m1_rm_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat32m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m4_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m4_f32m1_rm_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat32m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m8_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfredusum_vs_f32m8_f32m1_rm_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m1_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m1_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat64m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m2_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m2_f64m1_rm_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat64m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m4_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m4_f64m1_rm_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat64m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfredusum_vs_f64m8_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x double> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfredusum_vs_f64m8_f64m1_rm_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
index 85f787dd030d1a..0edb20720400ee 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_tum(vbool64_t mask, vfloat32m1_t ma
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_tum(vbool32_t mask, vfloat32m1_t ma
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_tum(vbool16_t mask, vfloat32m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_tum(vbool8_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_tum(vbool4_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_tum(vbool2_t mask, vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_tum(vbool2_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_tum(vbool64_t mask, vfloat64m1_t ma
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_tum(vbool32_t mask, vfloat64m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_tum(vbool16_t mask, vfloat64m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -220,10 +220,230 @@ vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_tum(vbool8_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_tum(vbool4_t mask, vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfwredosum_tum(mask, maskedoff, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1_rm_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16mf2_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_rm_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m2_f32m1_rm_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_rm_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_rm_tum(vbool2_t mask, vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m1_f64m1_rm_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m2_f64m1_rm_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m4_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m4_f64m1_rm_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m8_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_rm_tum(vbool4_t mask, vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredosum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
index 6bd3ae1e7624a4..b0a4cae7a6e84e 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
@@ -10,7 +10,7 @@
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -20,7 +20,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -30,7 +30,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -40,7 +40,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -50,7 +50,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -60,7 +60,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -70,7 +70,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_tu(vfloat32m1_t maskedoff, vfloat16m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -80,7 +80,7 @@ vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -90,7 +90,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -100,7 +100,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -110,7 +110,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -120,7 +120,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_tu(vfloat64m1_t maskedoff, vfloat32m
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -130,7 +130,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_tum(vbool64_t mask, vfloat32m1_t ma
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -140,7 +140,7 @@ vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_tum(vbool32_t mask, vfloat32m1_t ma
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -150,7 +150,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_tum(vbool16_t mask, vfloat32m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -160,7 +160,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_tum(vbool8_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -170,7 +170,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_tum(vbool4_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_tum(vbool2_t mask, vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
@@ -180,7 +180,7 @@ vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_tum(vbool2_t mask, vfloat32m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -190,7 +190,7 @@ vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_tum(vbool64_t mask, vfloat64m1_t ma
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -200,7 +200,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_tum(vbool32_t mask, vfloat64m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -210,7 +210,7 @@ vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_tum(vbool16_t mask, vfloat64m1_t mas
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
@@ -220,10 +220,230 @@ vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_tum(vbool8_t mask, vfloat64m1_t mask
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_tum(vbool4_t mask, vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
return __riscv_vfwredusum_tum(mask, maskedoff, vector, scalar, vl);
}
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1_rm_tu
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_rm_tu(vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tu(maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 1 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_rm_tum(vbool64_t mask, vfloat32m1_t maskedoff, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 2 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 4 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_rm_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 8 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_rm_tum(vbool8_t mask, vfloat32m1_t maskedoff, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 16 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_rm_tum(vbool4_t mask, vfloat32m1_t maskedoff, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[MASKEDOFF]], <vscale x 32 x half> [[VECTOR]], <vscale x 2 x float> [[SCALAR]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_rm_tum(vbool2_t mask, vfloat32m1_t maskedoff, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 1 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t maskedoff, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 2 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_rm_tum(vbool32_t mask, vfloat64m1_t maskedoff, vfloat32m1_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 4 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_rm_tum(vbool16_t mask, vfloat64m1_t maskedoff, vfloat32m2_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m4_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 8 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_rm_tum(vbool8_t mask, vfloat64m1_t maskedoff, vfloat32m4_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m8_f64m1_rm_tum
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[MASKEDOFF]], <vscale x 16 x float> [[VECTOR]], <vscale x 1 x double> [[SCALAR]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_rm_tum(vbool4_t mask, vfloat64m1_t maskedoff, vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+ return __riscv_vfwredusum_tum(mask, maskedoff, vector, scalar, __RISCV_FRM_RNE, vl);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfredosum-out-of-range.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfredosum-out-of-range.c
new file mode 100644
index 00000000000000..2a99737e065706
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfredosum-out-of-range.c
@@ -0,0 +1,26 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
+// RUN: -fsyntax-only -verify %s
+
+#include <riscv_vector.h>
+
+vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_rm(vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfredosum_vs_f32m1_f32m1_rm(vector, scalar, 5, vl);
+}
+
+vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfredosum_vs_f32m1_f32m1_rm_m(mask, vector, scalar, 5, vl);
+}
+
+vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfredosum_vs_f32m1_f32m1_rm_tu(maskedoff, vector, scalar, 5, vl);
+}
+
+vfloat32m1_t test_vfredosum_vs_f32m1_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfredosum_vs_f32m1_f32m1_rm_tum(mask, maskedoff, vector, scalar, 5, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfredusum-out-of-range.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfredusum-out-of-range.c
new file mode 100644
index 00000000000000..36faa0f60c425a
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfredusum-out-of-range.c
@@ -0,0 +1,26 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
+// RUN: -fsyntax-only -verify %s
+
+#include <riscv_vector.h>
+
+vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_rm(vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfredusum_vs_f32m1_f32m1_rm(vector, scalar, 5, vl);
+}
+
+vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfredusum_vs_f32m1_f32m1_rm_m(mask, vector, scalar, 5, vl);
+}
+
+vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfredusum_vs_f32m1_f32m1_rm_tu(maskedoff, vector, scalar, 5, vl);
+}
+
+vfloat32m1_t test_vfredusum_vs_f32m1_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfredusum_vs_f32m1_f32m1_rm_tum(mask, maskedoff, vector, scalar, 5, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwredosum-out-of-range.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwredosum-out-of-range.c
new file mode 100644
index 00000000000000..df35fda7b537f8
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwredosum-out-of-range.c
@@ -0,0 +1,26 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
+// RUN: -fsyntax-only -verify %s
+
+#include <riscv_vector.h>
+
+vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_rm(vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwredosum_vs_f16m1_f32m1_rm(vector, scalar, 5, vl);
+}
+
+vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_rm_m(vbool16_t mask, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwredosum_vs_f16m1_f32m1_rm_m(mask, vector, scalar, 5, vl);
+}
+
+vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwredosum_vs_f16m1_f32m1_rm_tu(maskedoff, vector, scalar, 5, vl);
+}
+
+vfloat32m1_t test_vfwredosum_vs_f16m1_f32m1_rm_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwredosum_vs_f16m1_f32m1_rm_tum(mask, maskedoff, vector, scalar, 5, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwredusum-out-of-range.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwredusum-out-of-range.c
new file mode 100644
index 00000000000000..555fcab4d4d014
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwredusum-out-of-range.c
@@ -0,0 +1,26 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
+// RUN: -fsyntax-only -verify %s
+
+#include <riscv_vector.h>
+
+vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_rm(vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwredusum_vs_f16m1_f32m1_rm(vector, scalar, 5, vl);
+}
+
+vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_rm_m(vbool16_t mask, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwredusum_vs_f16m1_f32m1_rm_m(mask, vector, scalar, 5, vl);
+}
+
+vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwredusum_vs_f16m1_f32m1_rm_tu(maskedoff, vector, scalar, 5, vl);
+}
+
+vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_rm_tum(vbool16_t mask, vfloat32m1_t maskedoff, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
+ // expected-error at +1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwredusum_vs_f16m1_f32m1_rm_tum(mask, maskedoff, vector, scalar, 5, vl);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 64d2d61e53e5c1..cfadbd6d2fa49c 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -887,6 +887,28 @@ let TargetPrefix = "riscv" in {
[IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 4;
}
+ // For Reduction ternary operations.
+ // For destination vector type is the same as first and third source vector.
+ // Input: (vector_in, vector_in, vector_in, frm, vl)
+ class RISCVReductionUnMaskedRoundingMode
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>,
+ llvm_anyint_ty, LLVMMatchType<2>],
+ [ImmArg<ArgIndex<3>>, IntrNoMem]>, RISCVVIntrinsic {
+ let VLOperand = 4;
+ }
+ // For Reduction ternary operations with mask.
+ // For destination vector type is the same as first and third source vector.
+ // The mask type come from second source vector.
+ // Input: (vector_in, vector_in, vector_in, mask, frm, vl)
+ class RISCVReductionMaskedRoundingMode
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>,
+ LLVMScalarOrSameVectorWidth<1, llvm_i1_ty>, llvm_anyint_ty,
+ LLVMMatchType<2>],
+ [ImmArg<ArgIndex<4>>, IntrNoMem]>, RISCVVIntrinsic {
+ let VLOperand = 5;
+ }
// For unary operations with scalar type output without mask
// Output: (scalar type)
// Input: (vector_in, vl)
@@ -1312,6 +1334,10 @@ let TargetPrefix = "riscv" in {
def "int_riscv_" # NAME : RISCVReductionUnMasked;
def "int_riscv_" # NAME # "_mask" : RISCVReductionMasked;
}
+ multiclass RISCVReductionRoundingMode {
+ def "int_riscv_" # NAME : RISCVReductionUnMaskedRoundingMode;
+ def "int_riscv_" # NAME # "_mask" : RISCVReductionMaskedRoundingMode;
+ }
multiclass RISCVMaskedUnarySOut {
def "int_riscv_" # NAME : RISCVMaskedUnarySOutUnMasked;
def "int_riscv_" # NAME # "_mask" : RISCVMaskedUnarySOutMasked;
@@ -1592,13 +1618,13 @@ let TargetPrefix = "riscv" in {
defm vwredsumu : RISCVReduction;
defm vwredsum : RISCVReduction;
- defm vfredosum : RISCVReduction;
- defm vfredusum : RISCVReduction;
+ defm vfredosum : RISCVReductionRoundingMode;
+ defm vfredusum : RISCVReductionRoundingMode;
defm vfredmin : RISCVReduction;
defm vfredmax : RISCVReduction;
- defm vfwredusum : RISCVReduction;
- defm vfwredosum : RISCVReduction;
+ defm vfwredusum : RISCVReductionRoundingMode;
+ defm vfwredosum : RISCVReductionRoundingMode;
def int_riscv_vmand: RISCVBinaryAAAUnMasked;
def int_riscv_vmnand: RISCVBinaryAAAUnMasked;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 8951d734cf86d9..f03d266e463204 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1290,6 +1290,28 @@ class VPseudoTernaryMaskPolicy<VReg RetClass,
let HasVecPolicyOp = 1;
}
+class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,
+ RegisterClass Op1Class,
+ DAGOperand Op2Class,
+ string Constraint> :
+ Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+ (ins GetVRegNoV0<RetClass>.R:$merge,
+ Op1Class:$rs2, Op2Class:$rs1,
+ VMaskOp:$vm,
+ ixlenimm:$rm,
+ AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ RISCVVPseudo {
+ let mayLoad = 0;
+ let mayStore = 0;
+ let hasSideEffects = 0;
+ let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
+ let HasVLOp = 1;
+ let HasSEWOp = 1;
+ let HasVecPolicyOp = 1;
+ let HasRoundModeOp = 1;
+ let UsesVXRM = 0;
+}
+
// Like VPseudoBinaryNoMask, but output can be V0.
class VPseudoBinaryMOutNoMask<VReg RetClass,
VReg Op1Class,
@@ -3230,6 +3252,25 @@ multiclass VPseudoTernaryWithTailPolicy<VReg RetClass,
}
}
+multiclass VPseudoTernaryWithTailPolicyRoundingMode<VReg RetClass,
+ RegisterClass Op1Class,
+ DAGOperand Op2Class,
+ LMULInfo MInfo,
+ int sew,
+ string Constraint = "",
+ bit Commutable = 0> {
+ let VLMul = MInfo.value in {
+ defvar mx = MInfo.MX;
+ let isCommutable = Commutable in
+ def "_" # mx # "_E" # sew
+ : VPseudoTernaryNoMaskWithPolicyRoundingMode<RetClass, Op1Class,
+ Op2Class, Constraint>;
+ def "_" # mx # "_E" # sew # "_MASK"
+ : VPseudoTernaryMaskPolicyRoundingMode<RetClass, Op1Class,
+ Op2Class, Constraint>;
+ }
+}
+
multiclass VPseudoTernaryWithPolicy<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
@@ -3595,12 +3636,14 @@ multiclass VPseudoVWRED_VS {
}
}
-multiclass VPseudoVFRED_VS {
+multiclass VPseudoVFRED_VS_RM {
foreach m = MxListF in {
defvar mx = m.MX;
foreach e = SchedSEWSet<mx, /*isF*/ 1>.val in {
defvar WriteVFRedV_From_MX_E = !cast<SchedWrite>("WriteVFRedV_From_" # mx # "_E" # e);
- defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
+ defm _VS
+ : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,
+ V_M1.vrclass, m, e>,
Sched<[WriteVFRedV_From_MX_E, ReadVFRedV, ReadVFRedV, ReadVFRedV,
ReadVMask]>;
}
@@ -3619,24 +3662,27 @@ multiclass VPseudoVFREDMINMAX_VS {
}
}
-multiclass VPseudoVFREDO_VS {
+multiclass VPseudoVFREDO_VS_RM {
foreach m = MxListF in {
defvar mx = m.MX;
foreach e = SchedSEWSet<mx, /*isF*/ 1>.val in {
defvar WriteVFRedOV_From_MX_E = !cast<SchedWrite>("WriteVFRedOV_From_" # mx # "_E" # e);
- defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
+ defm _VS : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,
+ V_M1.vrclass, m, e>,
Sched<[WriteVFRedOV_From_MX_E, ReadVFRedOV, ReadVFRedOV,
ReadVFRedOV, ReadVMask]>;
}
}
}
-multiclass VPseudoVFWRED_VS {
+multiclass VPseudoVFWRED_VS_RM {
foreach m = MxListFWRed in {
defvar mx = m.MX;
foreach e = SchedSEWSet<mx, /*isF*/ 1, /*isWidening*/ 1>.val in {
defvar WriteVFWRedV_From_MX_E = !cast<SchedWrite>("WriteVFWRedV_From_" # mx # "_E" # e);
- defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
+ defm _VS
+ : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,
+ V_M1.vrclass, m, e>,
Sched<[WriteVFWRedV_From_MX_E, ReadVFWRedV, ReadVFWRedV,
ReadVFWRedV, ReadVMask]>;
}
@@ -4553,6 +4599,30 @@ class VPatTernaryNoMaskTA<string intrinsic,
op2_kind:$rs2,
GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
+class VPatTernaryNoMaskTARoundingMode<string intrinsic,
+ string inst,
+ string kind,
+ ValueType result_type,
+ ValueType op1_type,
+ ValueType op2_type,
+ int log2sew,
+ LMULInfo vlmul,
+ VReg result_reg_class,
+ RegisterClass op1_reg_class,
+ DAGOperand op2_kind> :
+ Pat<(result_type (!cast<Intrinsic>(intrinsic)
+ (result_type result_reg_class:$rs3),
+ (op1_type op1_reg_class:$rs1),
+ (op2_type op2_kind:$rs2),
+ (XLenVT timm:$round),
+ VLOpFrag)),
+ (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew))
+ result_reg_class:$rs3,
+ (op1_type op1_reg_class:$rs1),
+ op2_kind:$rs2,
+ (XLenVT timm:$round),
+ GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
+
class VPatTernaryNoMaskWithPolicy<string intrinsic,
string inst,
string kind,
@@ -4701,6 +4771,33 @@ class VPatTernaryMaskTA<string intrinsic,
(mask_type V0),
GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
+class VPatTernaryMaskTARoundingMode<string intrinsic,
+ string inst,
+ string kind,
+ ValueType result_type,
+ ValueType op1_type,
+ ValueType op2_type,
+ ValueType mask_type,
+ int log2sew,
+ LMULInfo vlmul,
+ VReg result_reg_class,
+ RegisterClass op1_reg_class,
+ DAGOperand op2_kind> :
+ Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask")
+ (result_type result_reg_class:$rs3),
+ (op1_type op1_reg_class:$rs1),
+ (op2_type op2_kind:$rs2),
+ (mask_type V0),
+ (XLenVT timm:$round),
+ VLOpFrag)),
+ (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#!shl(1, log2sew)# "_MASK")
+ result_reg_class:$rs3,
+ (op1_type op1_reg_class:$rs1),
+ op2_kind:$rs2,
+ (mask_type V0),
+ (XLenVT timm:$round),
+ GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
+
multiclass VPatUnaryS_M<string intrinsic_name,
string inst> {
foreach mti = AllMasks in {
@@ -5674,6 +5771,26 @@ multiclass VPatTernaryTA<string intrinsic,
result_reg_class, op1_reg_class, op2_kind>;
}
+multiclass VPatTernaryTARoundingMode<string intrinsic,
+ string inst,
+ string kind,
+ ValueType result_type,
+ ValueType op1_type,
+ ValueType op2_type,
+ ValueType mask_type,
+ int log2sew,
+ LMULInfo vlmul,
+ VReg result_reg_class,
+ RegisterClass op1_reg_class,
+ DAGOperand op2_kind> {
+ def : VPatTernaryNoMaskTARoundingMode<intrinsic, inst, kind, result_type, op1_type,
+ op2_type, log2sew, vlmul, result_reg_class,
+ op1_reg_class, op2_kind>;
+ def : VPatTernaryMaskTARoundingMode<intrinsic, inst, kind, result_type, op1_type,
+ op2_type, mask_type, log2sew, vlmul,
+ result_reg_class, op1_reg_class, op2_kind>;
+}
+
multiclass VPatTernaryV_VV_AAXA<string intrinsic, string instruction,
list<VTypeInfo> vtilist> {
foreach vti = vtilist in
@@ -5863,6 +5980,26 @@ multiclass VPatReductionV_VS<string intrinsic, string instruction, bit IsFloat =
}
}
+multiclass VPatReductionV_VS_RM<string intrinsic, string instruction, bit IsFloat = 0> {
+ foreach vti = !if(IsFloat, NoGroupFloatVectors, NoGroupIntegerVectors) in {
+ defvar vectorM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # vti.SEW # "M1");
+ let Predicates = GetVTypePredicates<vti>.Predicates in
+ defm : VPatTernaryTARoundingMode<intrinsic, instruction, "VS",
+ vectorM1.Vector, vti.Vector,
+ vectorM1.Vector, vti.Mask,
+ vti.Log2SEW, vti.LMul,
+ VR, vti.RegClass, VR>;
+ }
+ foreach gvti = !if(IsFloat, GroupFloatVectors, GroupIntegerVectors) in {
+ let Predicates = GetVTypePredicates<gvti>.Predicates in
+ defm : VPatTernaryTARoundingMode<intrinsic, instruction, "VS",
+ gvti.VectorM1, gvti.Vector,
+ gvti.VectorM1, gvti.Mask,
+ gvti.Log2SEW, gvti.LMul,
+ VR, gvti.RegClass, VR>;
+ }
+}
+
multiclass VPatReductionW_VS<string intrinsic, string instruction, bit IsFloat = 0> {
foreach vti = !if(IsFloat, AllFloatVectors, AllIntegerVectors) in {
defvar wtiSEW = !mul(vti.SEW, 2);
@@ -5879,6 +6016,22 @@ multiclass VPatReductionW_VS<string intrinsic, string instruction, bit IsFloat =
}
}
+multiclass VPatReductionW_VS_RM<string intrinsic, string instruction, bit IsFloat = 0> {
+ foreach vti = !if(IsFloat, AllFloatVectors, AllIntegerVectors) in {
+ defvar wtiSEW = !mul(vti.SEW, 2);
+ if !le(wtiSEW, 64) then {
+ defvar wtiM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # wtiSEW # "M1");
+ let Predicates = GetVTypePredicates<vti>.Predicates in
+ defm : VPatTernaryTARoundingMode<intrinsic, instruction, "VS",
+ wtiM1.Vector, vti.Vector,
+ wtiM1.Vector, vti.Mask,
+ vti.Log2SEW, vti.LMul,
+ wtiM1.RegClass, vti.RegClass,
+ wtiM1.RegClass>;
+ }
+ }
+}
+
multiclass VPatConversionVI_VF<string intrinsic,
string instruction> {
foreach fvti = AllFloatVectors in {
@@ -6637,9 +6790,10 @@ let Predicates = [HasVInstructionsAnyF] in {
//===----------------------------------------------------------------------===//
// 14.3. Vector Single-Width Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
-let Uses = [FRM], mayRaiseFPException = true in {
-defm PseudoVFREDOSUM : VPseudoVFREDO_VS;
-defm PseudoVFREDUSUM : VPseudoVFRED_VS;
+let mayRaiseFPException = true,
+ hasSideEffects = 0 in {
+defm PseudoVFREDOSUM : VPseudoVFREDO_VS_RM;
+defm PseudoVFREDUSUM : VPseudoVFRED_VS_RM;
}
let mayRaiseFPException = true in {
defm PseudoVFREDMIN : VPseudoVFREDMINMAX_VS;
@@ -6650,10 +6804,10 @@ defm PseudoVFREDMAX : VPseudoVFREDMINMAX_VS;
// 14.4. Vector Widening Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
let IsRVVWideningReduction = 1,
- Uses = [FRM],
+ hasSideEffects = 0,
mayRaiseFPException = true in {
-defm PseudoVFWREDUSUM : VPseudoVFWRED_VS;
-defm PseudoVFWREDOSUM : VPseudoVFWRED_VS;
+defm PseudoVFWREDUSUM : VPseudoVFWRED_VS_RM;
+defm PseudoVFWREDOSUM : VPseudoVFWRED_VS_RM;
}
} // Predicates = [HasVInstructionsAnyF]
@@ -7278,16 +7432,16 @@ defm : VPatReductionW_VS<"int_riscv_vwredsum", "PseudoVWREDSUM">;
//===----------------------------------------------------------------------===//
// 14.3. Vector Single-Width Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
-defm : VPatReductionV_VS<"int_riscv_vfredosum", "PseudoVFREDOSUM", /*IsFloat=*/1>;
-defm : VPatReductionV_VS<"int_riscv_vfredusum", "PseudoVFREDUSUM", /*IsFloat=*/1>;
+defm : VPatReductionV_VS_RM<"int_riscv_vfredosum", "PseudoVFREDOSUM", /*IsFloat=*/1>;
+defm : VPatReductionV_VS_RM<"int_riscv_vfredusum", "PseudoVFREDUSUM", /*IsFloat=*/1>;
defm : VPatReductionV_VS<"int_riscv_vfredmin", "PseudoVFREDMIN", /*IsFloat=*/1>;
defm : VPatReductionV_VS<"int_riscv_vfredmax", "PseudoVFREDMAX", /*IsFloat=*/1>;
//===----------------------------------------------------------------------===//
// 14.4. Vector Widening Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
-defm : VPatReductionW_VS<"int_riscv_vfwredusum", "PseudoVFWREDUSUM", /*IsFloat=*/1>;
-defm : VPatReductionW_VS<"int_riscv_vfwredosum", "PseudoVFWREDOSUM", /*IsFloat=*/1>;
+defm : VPatReductionW_VS_RM<"int_riscv_vfwredusum", "PseudoVFWREDUSUM", /*IsFloat=*/1>;
+defm : VPatReductionW_VS_RM<"int_riscv_vfwredosum", "PseudoVFWREDOSUM", /*IsFloat=*/1>;
//===----------------------------------------------------------------------===//
// 15. Vector Mask Instructions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 06925ad9f3fa84..ab38b1b65f6f8b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -1381,6 +1381,39 @@ multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> {
}
}
+multiclass VPatReductionVL_RM<SDNode vop, string instruction_name, bit is_float> {
+ foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in {
+ defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1");
+ let Predicates = GetVTypePredicates<vti>.Predicates in {
+ def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge),
+ (vti.Vector vti.RegClass:$rs1), VR:$rs2,
+ (vti.Mask true_mask), VLOpFrag,
+ (XLenVT timm:$policy))),
+ (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW)
+ (vti_m1.Vector VR:$merge),
+ (vti.Vector vti.RegClass:$rs1),
+ (vti_m1.Vector VR:$rs2),
+ // Value to indicate no rounding mode change in
+ // RISCVInsertReadWriteCSR
+ FRM_DYN,
+ GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>;
+
+ def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge),
+ (vti.Vector vti.RegClass:$rs1), VR:$rs2,
+ (vti.Mask V0), VLOpFrag,
+ (XLenVT timm:$policy))),
+ (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK")
+ (vti_m1.Vector VR:$merge),
+ (vti.Vector vti.RegClass:$rs1),
+ (vti_m1.Vector VR:$rs2),
+ (vti.Mask V0),
+ // Value to indicate no rounding mode change in
+ // RISCVInsertReadWriteCSR
+ FRM_DYN,
+ GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>;
+ }
+ }
+}
multiclass VPatBinaryExtVL_WV_WX<SDNode op, PatFrags extop, string instruction_name> {
foreach vtiToWti = AllWidenableIntVectors in {
@@ -1459,6 +1492,41 @@ multiclass VPatWidenReductionVL<SDNode vop, PatFrags extop, string instruction_n
}
}
+multiclass VPatWidenReductionVL_RM<SDNode vop, PatFrags extop, string instruction_name, bit is_float> {
+ foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in {
+ defvar vti = vtiToWti.Vti;
+ defvar wti = vtiToWti.Wti;
+ defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1");
+ let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
+ GetVTypePredicates<wti>.Predicates) in {
+ def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge),
+ (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))),
+ VR:$rs2, (vti.Mask true_mask), VLOpFrag,
+ (XLenVT timm:$policy))),
+ (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW)
+ (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1),
+ (wti_m1.Vector VR:$rs2),
+ // Value to indicate no rounding mode change in
+ // RISCVInsertReadWriteCSR
+ FRM_DYN,
+ GPR:$vl, vti.Log2SEW,
+ (XLenVT timm:$policy))>;
+ def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge),
+ (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))),
+ VR:$rs2, (vti.Mask V0), VLOpFrag,
+ (XLenVT timm:$policy))),
+ (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK")
+ (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1),
+ (wti_m1.Vector VR:$rs2), (vti.Mask V0),
+ // Value to indicate no rounding mode change in
+ // RISCVInsertReadWriteCSR
+ FRM_DYN,
+ GPR:$vl, vti.Log2SEW,
+ (XLenVT timm:$policy))>;
+ }
+ }
+}
+
multiclass VPatWidenReductionVL_Ext_VL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> {
foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in {
defvar vti = vtiToWti.Vti;
@@ -1486,6 +1554,41 @@ multiclass VPatWidenReductionVL_Ext_VL<SDNode vop, PatFrags extop, string instru
}
}
+multiclass VPatWidenReductionVL_Ext_VL_RM<SDNode vop, PatFrags extop, string instruction_name, bit is_float> {
+ foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in {
+ defvar vti = vtiToWti.Vti;
+ defvar wti = vtiToWti.Wti;
+ defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1");
+ let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
+ GetVTypePredicates<wti>.Predicates) in {
+ def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge),
+ (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)),
+ VR:$rs2, (vti.Mask true_mask), VLOpFrag,
+ (XLenVT timm:$policy))),
+ (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW)
+ (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1),
+ (wti_m1.Vector VR:$rs2),
+ // Value to indicate no rounding mode change in
+ // RISCVInsertReadWriteCSR
+ FRM_DYN,
+ GPR:$vl, vti.Log2SEW,
+ (XLenVT timm:$policy))>;
+ def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge),
+ (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)),
+ VR:$rs2, (vti.Mask V0), VLOpFrag,
+ (XLenVT timm:$policy))),
+ (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK")
+ (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1),
+ (wti_m1.Vector VR:$rs2), (vti.Mask V0),
+ // Value to indicate no rounding mode change in
+ // RISCVInsertReadWriteCSR
+ FRM_DYN,
+ GPR:$vl, vti.Log2SEW,
+ (XLenVT timm:$policy))>;
+ }
+ }
+}
+
multiclass VPatBinaryFPWVL_VV_VF<SDNode vop, string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar vti = fvtiToFWti.Vti;
@@ -2518,16 +2621,22 @@ defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, sext_oneuse, "PseudoVWREDSUM",
defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_sext_vl_oneuse, "PseudoVWREDSUM", /*is_float*/0>;
// 14.3. Vector Single-Width Floating-Point Reduction Instructions
-defm : VPatReductionVL<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", /*is_float*/1>;
-defm : VPatReductionVL<rvv_vecreduce_FADD_vl, "PseudoVFREDUSUM", /*is_float*/1>;
+defm : VPatReductionVL_RM<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", /*is_float*/1>;
+defm : VPatReductionVL_RM<rvv_vecreduce_FADD_vl, "PseudoVFREDUSUM", /*is_float*/1>;
defm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", /*is_float*/1>;
defm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", /*is_float*/1>;
// 14.4. Vector Widening Floating-Point Reduction Instructions
-defm : VPatWidenReductionVL<rvv_vecreduce_SEQ_FADD_vl, fpext_oneuse, "PseudoVFWREDOSUM", /*is_float*/1>;
-defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_SEQ_FADD_vl, riscv_fpextend_vl_oneuse, "PseudoVFWREDOSUM", /*is_float*/1>;
-defm : VPatWidenReductionVL<rvv_vecreduce_FADD_vl, fpext_oneuse, "PseudoVFWREDUSUM", /*is_float*/1>;
-defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_FADD_vl, riscv_fpextend_vl_oneuse, "PseudoVFWREDUSUM", /*is_float*/1>;
+defm : VPatWidenReductionVL_RM<rvv_vecreduce_SEQ_FADD_vl, fpext_oneuse,
+ "PseudoVFWREDOSUM", /*is_float*/1>;
+defm : VPatWidenReductionVL_Ext_VL_RM<rvv_vecreduce_SEQ_FADD_vl,
+ riscv_fpextend_vl_oneuse,
+ "PseudoVFWREDOSUM", /*is_float*/1>;
+defm : VPatWidenReductionVL_RM<rvv_vecreduce_FADD_vl, fpext_oneuse,
+ "PseudoVFWREDUSUM", /*is_float*/1>;
+defm : VPatWidenReductionVL_Ext_VL_RM<rvv_vecreduce_FADD_vl,
+ riscv_fpextend_vl_oneuse,
+ "PseudoVFWREDUSUM", /*is_float*/1>;
// 15. Vector Mask Instructions
diff --git a/llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll b/llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
index 75ee82a2731b88..941653848183b3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
@@ -724,7 +724,7 @@ declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16(
<vscale x 4 x half>,
<vscale x 1 x half>,
<vscale x 4 x half>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 1 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16:
@@ -737,7 +737,7 @@ entry:
<vscale x 4 x half> undef,
<vscale x 1 x half> %0,
<vscale x 4 x half> %1,
- iXLen %2)
+ iXLen 7, iXLen %2)
ret <vscale x 4 x half> %a
}
@@ -746,7 +746,7 @@ declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16(
<vscale x 4 x half>,
<vscale x 1 x half>,
<vscale x 4 x half>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 1 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv1f16_nxv4f16:
@@ -759,7 +759,7 @@ entry:
<vscale x 4 x half> undef,
<vscale x 1 x half> %0,
<vscale x 4 x half> %1,
- iXLen %2)
+ iXLen 7, iXLen %2)
ret <vscale x 4 x half> %a
}
@@ -812,7 +812,7 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16(
<vscale x 2 x float>,
<vscale x 1 x half>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 1 x half> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32:
@@ -825,7 +825,7 @@ entry:
<vscale x 2 x float> undef,
<vscale x 1 x half> %0,
<vscale x 2 x float> %1,
- iXLen %2)
+ iXLen 7, iXLen %2)
ret <vscale x 2 x float> %a
}
@@ -833,7 +833,7 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16(
<vscale x 2 x float>,
<vscale x 1 x half>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredusum_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 1 x half> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv1f16_nxv2f32:
@@ -846,7 +846,7 @@ entry:
<vscale x 2 x float> undef,
<vscale x 1 x half> %0,
<vscale x 2 x float> %1,
- iXLen %2)
+ iXLen 7, iXLen %2)
ret <vscale x 2 x float> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll b/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
index 6d49023f6d5252..c8cb1d592f0b3f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
@@ -7,20 +7,22 @@ declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16(
<vscale x 4 x half>,
<vscale x 1 x half>,
<vscale x 4 x half>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16(
<vscale x 4 x half> %0,
<vscale x 1 x half> %1,
<vscale x 4 x half> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 4 x half> %a
}
@@ -30,13 +32,15 @@ declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.nxv1i1(
<vscale x 1 x half>,
<vscale x 4 x half>,
<vscale x 1 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.nxv1i1(
@@ -44,7 +48,7 @@ entry:
<vscale x 1 x half> %1,
<vscale x 4 x half> %2,
<vscale x 1 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 4 x half> %a
}
@@ -53,20 +57,22 @@ declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16(
<vscale x 4 x half>,
<vscale x 2 x half>,
<vscale x 4 x half>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16(
<vscale x 4 x half> %0,
<vscale x 2 x half> %1,
<vscale x 4 x half> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 4 x half> %a
}
@@ -76,13 +82,15 @@ declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.nxv2i1(
<vscale x 2 x half>,
<vscale x 4 x half>,
<vscale x 2 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.nxv2i1(
@@ -90,7 +98,7 @@ entry:
<vscale x 2 x half> %1,
<vscale x 4 x half> %2,
<vscale x 2 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 4 x half> %a
}
@@ -99,20 +107,22 @@ declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x half>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 4 x half> %a
}
@@ -122,13 +132,15 @@ declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.nxv4i1(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.nxv4i1(
@@ -136,7 +148,7 @@ entry:
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
<vscale x 4 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 4 x half> %a
}
@@ -145,20 +157,22 @@ declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16(
<vscale x 4 x half>,
<vscale x 8 x half>,
<vscale x 4 x half>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v10, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16(
<vscale x 4 x half> %0,
<vscale x 8 x half> %1,
<vscale x 4 x half> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 4 x half> %a
}
@@ -168,13 +182,15 @@ declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.nxv8i1(
<vscale x 8 x half>,
<vscale x 4 x half>,
<vscale x 8 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.nxv8i1(
@@ -182,7 +198,7 @@ entry:
<vscale x 8 x half> %1,
<vscale x 4 x half> %2,
<vscale x 8 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 4 x half> %a
}
@@ -191,20 +207,22 @@ declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16(
<vscale x 4 x half>,
<vscale x 16 x half>,
<vscale x 4 x half>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v12, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16(
<vscale x 4 x half> %0,
<vscale x 16 x half> %1,
<vscale x 4 x half> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 4 x half> %a
}
@@ -214,13 +232,15 @@ declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.nxv16i1(
<vscale x 16 x half>,
<vscale x 4 x half>,
<vscale x 16 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.nxv16i1(
@@ -228,7 +248,7 @@ entry:
<vscale x 16 x half> %1,
<vscale x 4 x half> %2,
<vscale x 16 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 4 x half> %a
}
@@ -237,20 +257,22 @@ declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16(
<vscale x 4 x half>,
<vscale x 32 x half>,
<vscale x 4 x half>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v16, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16(
<vscale x 4 x half> %0,
<vscale x 32 x half> %1,
<vscale x 4 x half> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 4 x half> %a
}
@@ -260,13 +282,15 @@ declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.nxv32i1(
<vscale x 32 x half>,
<vscale x 4 x half>,
<vscale x 32 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.nxv32i1(
@@ -274,7 +298,7 @@ entry:
<vscale x 32 x half> %1,
<vscale x 4 x half> %2,
<vscale x 32 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 4 x half> %a
}
@@ -283,20 +307,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32(
<vscale x 2 x float>,
<vscale x 1 x float>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32(
<vscale x 2 x float> %0,
<vscale x 1 x float> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -306,13 +332,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.nxv1i1(
<vscale x 1 x float>,
<vscale x 2 x float>,
<vscale x 1 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.nxv1i1(
@@ -320,7 +348,7 @@ entry:
<vscale x 1 x float> %1,
<vscale x 2 x float> %2,
<vscale x 1 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -329,20 +357,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -352,13 +382,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.nxv2i1(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.nxv2i1(
@@ -366,7 +398,7 @@ entry:
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
<vscale x 2 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -375,20 +407,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32(
<vscale x 2 x float>,
<vscale x 4 x float>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v10, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32(
<vscale x 2 x float> %0,
<vscale x 4 x float> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -398,13 +432,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.nxv4i1(
<vscale x 4 x float>,
<vscale x 2 x float>,
<vscale x 4 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.nxv4i1(
@@ -412,7 +448,7 @@ entry:
<vscale x 4 x float> %1,
<vscale x 2 x float> %2,
<vscale x 4 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -421,20 +457,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32(
<vscale x 2 x float>,
<vscale x 8 x float>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v12, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32(
<vscale x 2 x float> %0,
<vscale x 8 x float> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -444,13 +482,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.nxv8i1(
<vscale x 8 x float>,
<vscale x 2 x float>,
<vscale x 8 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.nxv8i1(
@@ -458,7 +498,7 @@ entry:
<vscale x 8 x float> %1,
<vscale x 2 x float> %2,
<vscale x 8 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -467,20 +507,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32(
<vscale x 2 x float>,
<vscale x 16 x float>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v16, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32(
<vscale x 2 x float> %0,
<vscale x 16 x float> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -490,13 +532,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.nxv16i1
<vscale x 16 x float>,
<vscale x 2 x float>,
<vscale x 16 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.nxv16i1(
@@ -504,7 +548,7 @@ entry:
<vscale x 16 x float> %1,
<vscale x 2 x float> %2,
<vscale x 16 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -513,20 +557,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -536,13 +582,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.nxv1i1(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.nxv1i1(
@@ -550,7 +598,7 @@ entry:
<vscale x 1 x double> %1,
<vscale x 1 x double> %2,
<vscale x 1 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
@@ -559,20 +607,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64(
<vscale x 1 x double>,
<vscale x 2 x double>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v10, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64(
<vscale x 1 x double> %0,
<vscale x 2 x double> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -582,13 +632,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.nxv2i1(
<vscale x 2 x double>,
<vscale x 1 x double>,
<vscale x 2 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.nxv2i1(
@@ -596,7 +648,7 @@ entry:
<vscale x 2 x double> %1,
<vscale x 1 x double> %2,
<vscale x 2 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
@@ -605,20 +657,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64(
<vscale x 1 x double>,
<vscale x 4 x double>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v12, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64(
<vscale x 1 x double> %0,
<vscale x 4 x double> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -628,13 +682,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.nxv4i1(
<vscale x 4 x double>,
<vscale x 1 x double>,
<vscale x 4 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.nxv4i1(
@@ -642,7 +698,7 @@ entry:
<vscale x 4 x double> %1,
<vscale x 1 x double> %2,
<vscale x 4 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
@@ -651,20 +707,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64(
<vscale x 1 x double>,
<vscale x 8 x double>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v16, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64(
<vscale x 1 x double> %0,
<vscale x 8 x double> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -674,13 +732,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.nxv8i1(
<vscale x 8 x double>,
<vscale x 1 x double>,
<vscale x 8 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.nxv8i1(
@@ -688,7 +748,7 @@ entry:
<vscale x 8 x double> %1,
<vscale x 1 x double> %2,
<vscale x 8 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll b/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
index f72aed34226ee3..c0514e26640491 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
@@ -7,20 +7,22 @@ declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16(
<vscale x 4 x half>,
<vscale x 1 x half>,
<vscale x 4 x half>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16(
<vscale x 4 x half> %0,
<vscale x 1 x half> %1,
<vscale x 4 x half> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 4 x half> %a
}
@@ -30,13 +32,15 @@ declare <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.nxv1i1(
<vscale x 1 x half>,
<vscale x 4 x half>,
<vscale x 1 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.nxv1i1(
@@ -44,7 +48,7 @@ entry:
<vscale x 1 x half> %1,
<vscale x 4 x half> %2,
<vscale x 1 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 4 x half> %a
}
@@ -53,20 +57,22 @@ declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16(
<vscale x 4 x half>,
<vscale x 2 x half>,
<vscale x 4 x half>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16(
<vscale x 4 x half> %0,
<vscale x 2 x half> %1,
<vscale x 4 x half> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 4 x half> %a
}
@@ -76,13 +82,15 @@ declare <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.nxv2i1(
<vscale x 2 x half>,
<vscale x 4 x half>,
<vscale x 2 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.nxv2i1(
@@ -90,7 +98,7 @@ entry:
<vscale x 2 x half> %1,
<vscale x 4 x half> %2,
<vscale x 2 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 4 x half> %a
}
@@ -99,20 +107,22 @@ declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x half>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 4 x half> %a
}
@@ -122,13 +132,15 @@ declare <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.nxv4i1(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.nxv4i1(
@@ -136,7 +148,7 @@ entry:
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
<vscale x 4 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 4 x half> %a
}
@@ -145,20 +157,22 @@ declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16(
<vscale x 4 x half>,
<vscale x 8 x half>,
<vscale x 4 x half>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v10, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16(
<vscale x 4 x half> %0,
<vscale x 8 x half> %1,
<vscale x 4 x half> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 4 x half> %a
}
@@ -168,13 +182,15 @@ declare <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.nxv8i1(
<vscale x 8 x half>,
<vscale x 4 x half>,
<vscale x 8 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v10, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.nxv8i1(
@@ -182,7 +198,7 @@ entry:
<vscale x 8 x half> %1,
<vscale x 4 x half> %2,
<vscale x 8 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 4 x half> %a
}
@@ -191,20 +207,22 @@ declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16(
<vscale x 4 x half>,
<vscale x 16 x half>,
<vscale x 4 x half>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v12, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16(
<vscale x 4 x half> %0,
<vscale x 16 x half> %1,
<vscale x 4 x half> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 4 x half> %a
}
@@ -214,13 +232,15 @@ declare <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.nxv16i1(
<vscale x 16 x half>,
<vscale x 4 x half>,
<vscale x 16 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v12, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.nxv16i1(
@@ -228,7 +248,7 @@ entry:
<vscale x 16 x half> %1,
<vscale x 4 x half> %2,
<vscale x 16 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 4 x half> %a
}
@@ -237,20 +257,22 @@ declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16(
<vscale x 4 x half>,
<vscale x 32 x half>,
<vscale x 4 x half>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v16, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16(
<vscale x 4 x half> %0,
<vscale x 32 x half> %1,
<vscale x 4 x half> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 4 x half> %a
}
@@ -260,13 +282,15 @@ declare <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.nxv32i1(
<vscale x 32 x half>,
<vscale x 4 x half>,
<vscale x 32 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v16, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.nxv32i1(
@@ -274,7 +298,7 @@ entry:
<vscale x 32 x half> %1,
<vscale x 4 x half> %2,
<vscale x 32 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 4 x half> %a
}
@@ -283,20 +307,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32(
<vscale x 2 x float>,
<vscale x 1 x float>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredusum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32(
<vscale x 2 x float> %0,
<vscale x 1 x float> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -306,13 +332,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.nxv1i1(
<vscale x 1 x float>,
<vscale x 2 x float>,
<vscale x 1 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredusum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.nxv1i1(
@@ -320,7 +348,7 @@ entry:
<vscale x 1 x float> %1,
<vscale x 2 x float> %2,
<vscale x 1 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -329,20 +357,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredusum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -352,13 +382,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.nxv2i1(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredusum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.nxv2i1(
@@ -366,7 +398,7 @@ entry:
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
<vscale x 2 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -375,20 +407,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32(
<vscale x 2 x float>,
<vscale x 4 x float>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredusum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v10, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32(
<vscale x 2 x float> %0,
<vscale x 4 x float> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -398,13 +432,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.nxv4i1(
<vscale x 4 x float>,
<vscale x 2 x float>,
<vscale x 4 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredusum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v10, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.nxv4i1(
@@ -412,7 +448,7 @@ entry:
<vscale x 4 x float> %1,
<vscale x 2 x float> %2,
<vscale x 4 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -421,20 +457,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32(
<vscale x 2 x float>,
<vscale x 8 x float>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredusum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v12, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32(
<vscale x 2 x float> %0,
<vscale x 8 x float> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -444,13 +482,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.nxv8i1(
<vscale x 8 x float>,
<vscale x 2 x float>,
<vscale x 8 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredusum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v12, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.nxv8i1(
@@ -458,7 +498,7 @@ entry:
<vscale x 8 x float> %1,
<vscale x 2 x float> %2,
<vscale x 8 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -467,20 +507,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32(
<vscale x 2 x float>,
<vscale x 16 x float>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredusum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v16, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32(
<vscale x 2 x float> %0,
<vscale x 16 x float> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -490,13 +532,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.nxv16i1
<vscale x 16 x float>,
<vscale x 2 x float>,
<vscale x 16 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfredusum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v16, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.nxv16i1(
@@ -504,7 +548,7 @@ entry:
<vscale x 16 x float> %1,
<vscale x 2 x float> %2,
<vscale x 16 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -513,20 +557,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredusum_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -536,13 +582,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.nxv1i1(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredusum_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.nxv1i1(
@@ -550,7 +598,7 @@ entry:
<vscale x 1 x double> %1,
<vscale x 1 x double> %2,
<vscale x 1 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
@@ -559,20 +607,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64(
<vscale x 1 x double>,
<vscale x 2 x double>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredusum_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v10, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64(
<vscale x 1 x double> %0,
<vscale x 2 x double> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -582,13 +632,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.nxv2i1(
<vscale x 2 x double>,
<vscale x 1 x double>,
<vscale x 2 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredusum_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v10, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.nxv2i1(
@@ -596,7 +648,7 @@ entry:
<vscale x 2 x double> %1,
<vscale x 1 x double> %2,
<vscale x 2 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
@@ -605,20 +657,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64(
<vscale x 1 x double>,
<vscale x 4 x double>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredusum_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v12, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64(
<vscale x 1 x double> %0,
<vscale x 4 x double> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -628,13 +682,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.nxv4i1(
<vscale x 4 x double>,
<vscale x 1 x double>,
<vscale x 4 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredusum_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v12, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.nxv4i1(
@@ -642,7 +698,7 @@ entry:
<vscale x 4 x double> %1,
<vscale x 1 x double> %2,
<vscale x 4 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
@@ -651,20 +707,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64(
<vscale x 1 x double>,
<vscale x 8 x double>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredusum_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v16, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64(
<vscale x 1 x double> %0,
<vscale x 8 x double> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -674,13 +732,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.nxv8i1(
<vscale x 8 x double>,
<vscale x 1 x double>,
<vscale x 8 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfredusum_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfredusum.vs v8, v16, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.nxv8i1(
@@ -688,7 +748,7 @@ entry:
<vscale x 8 x double> %1,
<vscale x 1 x double> %2,
<vscale x 8 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
index c850c303592cd3..d2396b20e10a98 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
@@ -7,20 +7,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16(
<vscale x 2 x float>,
<vscale x 1 x half>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16(
<vscale x 2 x float> %0,
<vscale x 1 x half> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -30,13 +32,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32
<vscale x 1 x half>,
<vscale x 2 x float>,
<vscale x 1 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32(
@@ -44,7 +48,7 @@ entry:
<vscale x 1 x half> %1,
<vscale x 2 x float> %2,
<vscale x 1 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -53,20 +57,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16(
<vscale x 2 x float>,
<vscale x 2 x half>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16(
<vscale x 2 x float> %0,
<vscale x 2 x half> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -76,13 +82,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32
<vscale x 2 x half>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32(
@@ -90,7 +98,7 @@ entry:
<vscale x 2 x half> %1,
<vscale x 2 x float> %2,
<vscale x 2 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -99,20 +107,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16(
<vscale x 2 x float>,
<vscale x 4 x half>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16(
<vscale x 2 x float> %0,
<vscale x 4 x half> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -122,13 +132,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32
<vscale x 4 x half>,
<vscale x 2 x float>,
<vscale x 4 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32(
@@ -136,7 +148,7 @@ entry:
<vscale x 4 x half> %1,
<vscale x 2 x float> %2,
<vscale x 4 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -145,20 +157,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16(
<vscale x 2 x float>,
<vscale x 8 x half>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v10, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16(
<vscale x 2 x float> %0,
<vscale x 8 x half> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -168,13 +182,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32
<vscale x 8 x half>,
<vscale x 2 x float>,
<vscale x 8 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32(
@@ -182,7 +198,7 @@ entry:
<vscale x 8 x half> %1,
<vscale x 2 x float> %2,
<vscale x 8 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -191,20 +207,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16(
<vscale x 2 x float>,
<vscale x 16 x half>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v12, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16(
<vscale x 2 x float> %0,
<vscale x 16 x half> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -214,13 +232,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f3
<vscale x 16 x half>,
<vscale x 2 x float>,
<vscale x 16 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f32(
@@ -228,7 +248,7 @@ entry:
<vscale x 16 x half> %1,
<vscale x 2 x float> %2,
<vscale x 16 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -237,20 +257,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16(
<vscale x 2 x float>,
<vscale x 32 x half>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v16, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16(
<vscale x 2 x float> %0,
<vscale x 32 x half> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -260,13 +282,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16(
<vscale x 32 x half>,
<vscale x 2 x float>,
<vscale x 32 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16(
@@ -274,7 +298,7 @@ entry:
<vscale x 32 x half> %1,
<vscale x 2 x float> %2,
<vscale x 32 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -283,20 +307,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32(
<vscale x 1 x double>,
<vscale x 1 x float>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32(
<vscale x 1 x double> %0,
<vscale x 1 x float> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -306,13 +332,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f6
<vscale x 1 x float>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f64(
@@ -320,7 +348,7 @@ entry:
<vscale x 1 x float> %1,
<vscale x 1 x double> %2,
<vscale x 1 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
@@ -329,20 +357,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32(
<vscale x 1 x double>,
<vscale x 2 x float>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32(
<vscale x 1 x double> %0,
<vscale x 2 x float> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -352,13 +382,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f6
<vscale x 2 x float>,
<vscale x 1 x double>,
<vscale x 2 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f64(
@@ -366,7 +398,7 @@ entry:
<vscale x 2 x float> %1,
<vscale x 1 x double> %2,
<vscale x 2 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
@@ -375,20 +407,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32(
<vscale x 1 x double>,
<vscale x 4 x float>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v10, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32(
<vscale x 1 x double> %0,
<vscale x 4 x float> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -398,13 +432,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f6
<vscale x 4 x float>,
<vscale x 1 x double>,
<vscale x 4 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f64(
@@ -412,7 +448,7 @@ entry:
<vscale x 4 x float> %1,
<vscale x 1 x double> %2,
<vscale x 4 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
@@ -421,20 +457,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32(
<vscale x 1 x double>,
<vscale x 8 x float>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v12, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32(
<vscale x 1 x double> %0,
<vscale x 8 x float> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -444,13 +482,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f6
<vscale x 8 x float>,
<vscale x 1 x double>,
<vscale x 8 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f64(
@@ -458,7 +498,7 @@ entry:
<vscale x 8 x float> %1,
<vscale x 1 x double> %2,
<vscale x 8 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
@@ -467,20 +507,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32(
<vscale x 1 x double>,
<vscale x 16 x float>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v16, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32(
<vscale x 1 x double> %0,
<vscale x 16 x float> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -490,13 +532,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.nxv1f
<vscale x 16 x float>,
<vscale x 1 x double>,
<vscale x 16 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.nxv1f64(
@@ -504,7 +548,7 @@ entry:
<vscale x 16 x float> %1,
<vscale x 1 x double> %2,
<vscale x 16 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
index 77df494ccd402b..53a39d441c806d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
@@ -7,20 +7,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16(
<vscale x 2 x float>,
<vscale x 1 x half>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredusum_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv1f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16(
<vscale x 2 x float> %0,
<vscale x 1 x half> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -30,13 +32,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.nxv2f32
<vscale x 1 x half>,
<vscale x 2 x float>,
<vscale x 1 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv1f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.nxv2f32(
@@ -44,7 +48,7 @@ entry:
<vscale x 1 x half> %1,
<vscale x 2 x float> %2,
<vscale x 1 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -53,20 +57,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16(
<vscale x 2 x float>,
<vscale x 2 x half>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredusum_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16(
<vscale x 2 x float> %0,
<vscale x 2 x half> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -76,13 +82,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.nxv2f32
<vscale x 2 x half>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.nxv2f32(
@@ -90,7 +98,7 @@ entry:
<vscale x 2 x half> %1,
<vscale x 2 x float> %2,
<vscale x 2 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -99,20 +107,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16(
<vscale x 2 x float>,
<vscale x 4 x half>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredusum_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv4f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16(
<vscale x 2 x float> %0,
<vscale x 4 x half> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -122,13 +132,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.nxv2f32
<vscale x 4 x half>,
<vscale x 2 x float>,
<vscale x 4 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv4f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.nxv2f32(
@@ -136,7 +148,7 @@ entry:
<vscale x 4 x half> %1,
<vscale x 2 x float> %2,
<vscale x 4 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -145,20 +157,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16(
<vscale x 2 x float>,
<vscale x 8 x half>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredusum_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv8f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v10, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16(
<vscale x 2 x float> %0,
<vscale x 8 x half> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -168,13 +182,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.nxv2f32
<vscale x 8 x half>,
<vscale x 2 x float>,
<vscale x 8 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv8f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v10, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.nxv2f32(
@@ -182,7 +198,7 @@ entry:
<vscale x 8 x half> %1,
<vscale x 2 x float> %2,
<vscale x 8 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -191,20 +207,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16(
<vscale x 2 x float>,
<vscale x 16 x half>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredusum_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv16f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v12, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16(
<vscale x 2 x float> %0,
<vscale x 16 x half> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -214,13 +232,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.nxv2f3
<vscale x 16 x half>,
<vscale x 2 x float>,
<vscale x 16 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv16f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v12, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.nxv2f32(
@@ -228,7 +248,7 @@ entry:
<vscale x 16 x half> %1,
<vscale x 2 x float> %2,
<vscale x 16 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -237,20 +257,22 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16(
<vscale x 2 x float>,
<vscale x 32 x half>,
<vscale x 2 x float>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredusum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv32f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v16, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16(
<vscale x 2 x float> %0,
<vscale x 32 x half> %1,
<vscale x 2 x float> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -260,13 +282,15 @@ declare <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16(
<vscale x 32 x half>,
<vscale x 2 x float>,
<vscale x 32 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv32f16_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v16, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16(
@@ -274,7 +298,7 @@ entry:
<vscale x 32 x half> %1,
<vscale x 2 x float> %2,
<vscale x 32 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 2 x float> %a
}
@@ -283,20 +307,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32(
<vscale x 1 x double>,
<vscale x 1 x float>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredusum_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv1f64_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32(
<vscale x 1 x double> %0,
<vscale x 1 x float> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -306,13 +332,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.nxv1f6
<vscale x 1 x float>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredusum_mask_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv1f64_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.nxv1f64(
@@ -320,7 +348,7 @@ entry:
<vscale x 1 x float> %1,
<vscale x 1 x double> %2,
<vscale x 1 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
@@ -329,20 +357,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32(
<vscale x 1 x double>,
<vscale x 2 x float>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredusum_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv1f64_nxv2f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v9, v10
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32(
<vscale x 1 x double> %0,
<vscale x 2 x float> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -352,13 +382,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.nxv1f6
<vscale x 2 x float>,
<vscale x 1 x double>,
<vscale x 2 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredusum_mask_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv1f64_nxv2f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v9, v10, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.nxv1f64(
@@ -366,7 +398,7 @@ entry:
<vscale x 2 x float> %1,
<vscale x 1 x double> %2,
<vscale x 2 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
@@ -375,20 +407,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32(
<vscale x 1 x double>,
<vscale x 4 x float>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredusum_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv1f64_nxv4f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v10, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32(
<vscale x 1 x double> %0,
<vscale x 4 x float> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -398,13 +432,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.nxv1f6
<vscale x 4 x float>,
<vscale x 1 x double>,
<vscale x 4 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredusum_mask_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv1f64_nxv4f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v10, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.nxv1f64(
@@ -412,7 +448,7 @@ entry:
<vscale x 4 x float> %1,
<vscale x 1 x double> %2,
<vscale x 4 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
@@ -421,20 +457,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32(
<vscale x 1 x double>,
<vscale x 8 x float>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredusum_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv1f64_nxv8f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v12, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32(
<vscale x 1 x double> %0,
<vscale x 8 x float> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -444,13 +482,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.nxv1f6
<vscale x 8 x float>,
<vscale x 1 x double>,
<vscale x 8 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredusum_mask_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv1f64_nxv8f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v12, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.nxv1f64(
@@ -458,7 +498,7 @@ entry:
<vscale x 8 x float> %1,
<vscale x 1 x double> %2,
<vscale x 8 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
@@ -467,20 +507,22 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32(
<vscale x 1 x double>,
<vscale x 16 x float>,
<vscale x 1 x double>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredusum_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv1f64_nxv16f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v16, v9
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32(
<vscale x 1 x double> %0,
<vscale x 16 x float> %1,
<vscale x 1 x double> %2,
- iXLen %3)
+ iXLen 0, iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -490,13 +532,15 @@ declare <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.nxv1f
<vscale x 16 x float>,
<vscale x 1 x double>,
<vscale x 16 x i1>,
- iXLen);
+ iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfwredusum_mask_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv1f64_nxv16f32_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfwredusum.vs v8, v16, v9, v0.t
+; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.nxv1f64(
@@ -504,7 +548,7 @@ entry:
<vscale x 16 x float> %1,
<vscale x 1 x double> %2,
<vscale x 16 x i1> %3,
- iXLen %4)
+ iXLen 0, iXLen %4)
ret <vscale x 1 x double> %a
}
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