[PATCH] D155102: [Clang][RISCV] Align RVV intrinsic builtin names with the C intrinsics
Yueh-Ting (eop) Chen via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Wed Jul 12 10:38:46 PDT 2023
eopXD created this revision.
eopXD added a reviewer: craig.topper.
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Herald added a project: clang.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D155102
Files:
clang/lib/Sema/SemaChecking.cpp
clang/lib/Support/RISCVVIntrinsicUtils.cpp
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===================================================================
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -1071,10 +1071,7 @@
appendPolicySuffix("_mu");
else if (PolicyAttrs.isTAMAPolicy()) {
Name += "_m";
- if (HasPolicy)
- BuiltinName += "_tama";
- else
- BuiltinName += "_m";
+ BuiltinName += "_m";
} else
llvm_unreachable("Unhandled policy condition");
} else {
Index: clang/lib/Sema/SemaChecking.cpp
===================================================================
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -4734,24 +4734,24 @@
case RISCVVector::BI__builtin_rvv_vnclip_wx_tu:
case RISCVVector::BI__builtin_rvv_vnclipu_wv_tu:
case RISCVVector::BI__builtin_rvv_vnclipu_wx_tu:
- case RISCVVector::BI__builtin_rvv_vaaddu_vv_tama:
- case RISCVVector::BI__builtin_rvv_vaaddu_vx_tama:
- case RISCVVector::BI__builtin_rvv_vaadd_vv_tama:
- case RISCVVector::BI__builtin_rvv_vaadd_vx_tama:
- case RISCVVector::BI__builtin_rvv_vasubu_vv_tama:
- case RISCVVector::BI__builtin_rvv_vasubu_vx_tama:
- case RISCVVector::BI__builtin_rvv_vasub_vv_tama:
- case RISCVVector::BI__builtin_rvv_vasub_vx_tama:
- case RISCVVector::BI__builtin_rvv_vsmul_vv_tama:
- case RISCVVector::BI__builtin_rvv_vsmul_vx_tama:
- case RISCVVector::BI__builtin_rvv_vssra_vv_tama:
- case RISCVVector::BI__builtin_rvv_vssra_vx_tama:
- case RISCVVector::BI__builtin_rvv_vssrl_vv_tama:
- case RISCVVector::BI__builtin_rvv_vssrl_vx_tama:
- case RISCVVector::BI__builtin_rvv_vnclip_wv_tama:
- case RISCVVector::BI__builtin_rvv_vnclip_wx_tama:
- case RISCVVector::BI__builtin_rvv_vnclipu_wv_tama:
- case RISCVVector::BI__builtin_rvv_vnclipu_wx_tama:
+ case RISCVVector::BI__builtin_rvv_vaaddu_vv_m:
+ case RISCVVector::BI__builtin_rvv_vaaddu_vx_m:
+ case RISCVVector::BI__builtin_rvv_vaadd_vv_m:
+ case RISCVVector::BI__builtin_rvv_vaadd_vx_m:
+ case RISCVVector::BI__builtin_rvv_vasubu_vv_m:
+ case RISCVVector::BI__builtin_rvv_vasubu_vx_m:
+ case RISCVVector::BI__builtin_rvv_vasub_vv_m:
+ case RISCVVector::BI__builtin_rvv_vasub_vx_m:
+ case RISCVVector::BI__builtin_rvv_vsmul_vv_m:
+ case RISCVVector::BI__builtin_rvv_vsmul_vx_m:
+ case RISCVVector::BI__builtin_rvv_vssra_vv_m:
+ case RISCVVector::BI__builtin_rvv_vssra_vx_m:
+ case RISCVVector::BI__builtin_rvv_vssrl_vv_m:
+ case RISCVVector::BI__builtin_rvv_vssrl_vx_m:
+ case RISCVVector::BI__builtin_rvv_vnclip_wv_m:
+ case RISCVVector::BI__builtin_rvv_vnclip_wx_m:
+ case RISCVVector::BI__builtin_rvv_vnclipu_wv_m:
+ case RISCVVector::BI__builtin_rvv_vnclipu_wx_m:
return SemaBuiltinConstantArgRange(TheCall, 3, 0, 3);
case RISCVVector::BI__builtin_rvv_vaaddu_vv_tum:
case RISCVVector::BI__builtin_rvv_vaaddu_vv_tumu:
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