[PATCH] D152658: [InstCombine] Change SimplifyDemandedVectorElts to use PoisonElts instead of UndefElts

[Juneyoung Lee via Phabricator via cfe-commits]

aqjune added a comment.

Hi, thanks for your hard work!



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Comment at: llvm/lib/Transforms/InstCombine/InstructionCombining.cpp:1653
-      if (ShMask[I] >= 0) {
-        assert(ShMask[I] < (int)NumElts && "Not expecting narrowing shuffle");
         Constant *NewCElt = NewVecC[ShMask[I]];
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This seems to be 


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Comment at: llvm/test/Transforms/InstCombine/vec_shuffle.ll:373
+; CHECK-NEXT: [[T2:%.*]] = shufflevector <2 x i32> [[T1]], <2 x i32> undef, <1 x i32> zeroinitializer
+; CHECK-NEXT:    ret <1 x i32> [[T2]]
 ;
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Do you have any idea about the reason of this regression? 


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Comment at: llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll:297
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i16
-; CHECK-NEXT:    [[TRUNC:%.*]] = insertelement <3 x i16> undef, i16 [[TMP1]], i64 1
+; CHECK-NEXT:    [[TRUNC:%.*]] = insertelement <3 x i16> <i16 undef, i16 poison, i16 undef>, i16 [[TMP1]], i64 1
 ; CHECK-NEXT:    ret <3 x i16> [[TRUNC]]
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This looks interesting - do you have idea how the undef elements are introduced?


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Comment at: llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll:451
 ; AVX2-NEXT:    [[TMP4:%.*]] = sdiv <2 x i32> [[TMP3]], <i32 8, i32 16>
-; AVX2-NEXT:    [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, i32 [[AB1]], i64 1
+; AVX2-NEXT:    [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 poison>, i32 [[AB1]], i64 1
 ; AVX2-NEXT:    [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
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Do you have any idea about why the 5'th element is undef, not poison?


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Comment at: llvm/test/Transforms/SLPVectorizer/X86/pr49081.ll:11
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <4 x float> poison, float [[TMP3]], i64 0
+; CHECK-NEXT:    [[TMP5:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> poison, <4 x i32> <i32 0, i32 0, i32 poison, i32 poison>
 ; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
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This change looks interesting, I think it is worth investigating why this happened.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152658/new/

https://reviews.llvm.org/D152658