[PATCH] D154635: [7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll:24
 ; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
+; CHECK-NEXT:    fsrm a0
 ; CHECK-NEXT:    ret
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This is concerning. This means the `vfcvt.f.x.v` is getting the modified rounding mode from `fsrmi a0, 3`. I think its functionally ok due to the inputs involved, but it still shouldn't be happening. Is the vfcvt.f.x.v missing its FRM implicit dependency for DYN?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154635/new/

https://reviews.llvm.org/D154635