[clang] 939f818 - [RISCV] Split __builtin_riscv_brev8 into _32 and _64 builtin.

[Craig Topper via cfe-commits]

Author: Craig Topper
Date: 2023-07-10T13:01:07-07:00
New Revision: 939f818a662a56a3b118e7e4b0656b6f7038adae

URL: https://github.com/llvm/llvm-project/commit/939f818a662a56a3b118e7e4b0656b6f7038adae
DIFF: https://github.com/llvm/llvm-project/commit/939f818a662a56a3b118e7e4b0656b6f7038adae.diff

LOG: [RISCV] Split __builtin_riscv_brev8 into _32 and _64 builtin.

Allow _32 builtin on RV64 since it only brev8+sext.w.

Part of an effort to remove 'long' to mean XLen from the builtin
interface.

Matches the proposal here https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D154683

Added: 
    

Modified: 
    clang/include/clang/Basic/BuiltinsRISCV.def
    clang/lib/CodeGen/CGBuiltin.cpp
    clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
    clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c

Removed: 
    


################################################################################
diff  --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def
index 5ea0b28e676910..4b4c7858d0fa7d 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.def
+++ b/clang/include/clang/Basic/BuiltinsRISCV.def
@@ -35,7 +35,8 @@ TARGET_BUILTIN(__builtin_riscv_xperm8_32, "iii", "nc", "zbkx,32bit")
 TARGET_BUILTIN(__builtin_riscv_xperm8_64, "WiWiWi", "nc", "zbkx,64bit")
 
 // Zbkb extension
-TARGET_BUILTIN(__builtin_riscv_brev8, "LiLi", "nc", "zbkb")
+TARGET_BUILTIN(__builtin_riscv_brev8_32, "ii", "nc", "zbkb")
+TARGET_BUILTIN(__builtin_riscv_brev8_64, "WiWi", "nc", "zbkb,64bit")
 TARGET_BUILTIN(__builtin_riscv_zip_32, "ZiZi", "nc", "zbkb,32bit")
 TARGET_BUILTIN(__builtin_riscv_unzip_32, "ZiZi", "nc", "zbkb,32bit")
 

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 97e031b9bb0618..088fb46faee5d8 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -20206,7 +20206,8 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
   case RISCV::BI__builtin_riscv_xperm4_64:
   case RISCV::BI__builtin_riscv_xperm8_32:
   case RISCV::BI__builtin_riscv_xperm8_64:
-  case RISCV::BI__builtin_riscv_brev8:
+  case RISCV::BI__builtin_riscv_brev8_32:
+  case RISCV::BI__builtin_riscv_brev8_64:
   case RISCV::BI__builtin_riscv_zip_32:
   case RISCV::BI__builtin_riscv_unzip_32: {
     switch (BuiltinID) {
@@ -20257,7 +20258,8 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
       break;
 
     // Zbkb
-    case RISCV::BI__builtin_riscv_brev8:
+    case RISCV::BI__builtin_riscv_brev8_32:
+    case RISCV::BI__builtin_riscv_brev8_64:
       ID = Intrinsic::riscv_brev8;
       break;
     case RISCV::BI__builtin_riscv_zip_32:

diff  --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
index 819280d2b0165d..d255ccb2cd2a6f 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
@@ -10,9 +10,9 @@
 // RV32ZBKB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[TMP0]])
 // RV32ZBKB-NEXT:    ret i32 [[TMP1]]
 //
-long brev8(long rs1)
+int brev8(int rs1)
 {
-  return __builtin_riscv_brev8(rs1);
+  return __builtin_riscv_brev8_32(rs1);
 }
 
 // RV32ZBKB-LABEL: @zip(

diff  --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
index 84a44e6a24629f..70a05d25ae7a14 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
@@ -2,7 +2,20 @@
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zbkb -emit-llvm %s -o - \
 // RUN:     | FileCheck %s  -check-prefix=RV64ZBKB
 
-// RV64ZBKB-LABEL: @brev8(
+// RV64ZBKB-LABEL: @brev8_32(
+// RV64ZBKB-NEXT:  entry:
+// RV64ZBKB-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBKB-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
+// RV64ZBKB-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
+// RV64ZBKB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.brev8.i32(i32 [[TMP0]])
+// RV64ZBKB-NEXT:    ret i32 [[TMP1]]
+//
+int brev8_32(int rs1)
+{
+  return __builtin_riscv_brev8_32(rs1);
+}
+
+// RV64ZBKB-LABEL: @brev8_64(
 // RV64ZBKB-NEXT:  entry:
 // RV64ZBKB-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
 // RV64ZBKB-NEXT:    store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
@@ -10,7 +23,7 @@
 // RV64ZBKB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.brev8.i64(i64 [[TMP0]])
 // RV64ZBKB-NEXT:    ret i64 [[TMP1]]
 //
-long brev8(long rs1)
+long brev8_64(long rs1)
 {
-  return __builtin_riscv_brev8(rs1);
+  return __builtin_riscv_brev8_64(rs1);
 }