[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs
Wang Pengcheng via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Mon Jul 10 02:13:24 PDT 2023
wangpc updated this revision to Diff 538547.
wangpc added a comment.
- Rebase.
- Fix PEI bugs of interrupt functions.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D70401/new/
https://reviews.llvm.org/D70401
Files:
clang/lib/Basic/Targets/RISCV.cpp
clang/lib/Basic/Targets/RISCV.h
clang/lib/CodeGen/CodeGenModule.cpp
clang/lib/CodeGen/TargetInfo.h
clang/lib/CodeGen/Targets/RISCV.cpp
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/test/CodeGen/RISCV/riscv32-abi.c
clang/test/CodeGen/RISCV/riscv32-ilp32e-error.c
clang/test/CodeGen/RISCV/riscv32-vararg.c
clang/test/CodeGen/RISCV/riscv64-abi.c
clang/test/CodeGen/RISCV/riscv64-vararg.c
clang/test/Preprocessor/riscv-target-features.c
llvm/include/llvm/Support/RISCVAttributes.h
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
llvm/lib/Target/RISCV/RISCVCallingConv.td
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
llvm/lib/Target/RISCV/RISCVFrameLowering.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll
llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll
llvm/test/CodeGen/RISCV/interrupt-attr.ll
llvm/test/CodeGen/RISCV/rv32e.ll
llvm/test/CodeGen/RISCV/rv64e.ll
llvm/test/CodeGen/RISCV/rve.ll
llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
llvm/test/CodeGen/RISCV/stack-realignment.ll
llvm/test/CodeGen/RISCV/target-abi-valid.ll
llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
llvm/test/CodeGen/RISCV/vararg.ll
llvm/test/MC/RISCV/option-invalid.s
llvm/test/MC/RISCV/target-abi-invalid.s
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