[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

[Zixuan Wu via Phabricator via cfe-commits]

zixuan-wu added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:908
 
     static const MCPhysReg CSRegs[] = { RISCV::X1,      /* ra */
       RISCV::X5, RISCV::X6, RISCV::X7,                  /* t0-t2 */
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Hi, @wangpc it's hidden bug that out of range registers are saved/restored in prologue/epilogue


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70401/new/

https://reviews.llvm.org/D70401