[PATCH] D147732: [AMDGPU] Add type mangling for {read, write, readfirst, perm}lane intrinsics

[Jeffrey Byrnes via Phabricator via cfe-commits]

jrbyrnes added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp:187
 
+Value *AMDGPULateCodeGenPrepare::buildLegalLaneIntrinsic(
+    IRBuilder<> &B, Intrinsic::ID IID, Value *Data0, Value *Data1, Value *Lane0,
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arsenm wrote:
> You're not relying on this for correctness are you? This is an optimization pass, you can't lower here. You also shouldn't need to handle this in the IR, it should codegen normally 
This is the legalization for non 32bit types -- I don't exactly know why it wasn't handled via the normal codegen / selection process. @nhaehnle , I believe you tried this in https://reviews.llvm.org/D86154 -- do you happen to remember why we do legalization this way? If not, I'll rework the approach.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147732/new/

https://reviews.llvm.org/D147732