[PATCH] D154629: [2/8][RISCV] Add rounding mode control variant for vfwadd, vfwsub

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:14
 #include "RISCVInstrInfo.h"
+#include "MCTargetDesc/RISCVBaseInfo.h"
 #include "MCTargetDesc/RISCVMatInt.h"
----------------
RISCV.h already includes this.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:2517
+  case CASE_WIDEOP_OPCODE_LMULS_MF4(FWSUB_WV): {
+    assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) &&
+           MI.getNumExplicitOperands() == 7 &&
----------------
This is a lot of code duplication. Can't we add a couple ifs to the existing code?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154629/new/

https://reviews.llvm.org/D154629