[PATCH] D154635: [RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added reviewers: craig.topper, reames, kito-cheng, rogfer01, frasercrmck.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, wangpc, MaskRay.
Herald added projects: clang, LLVM.

Depends on D154634 <https://reviews.llvm.org/D154634>

vfcvt_x_f, vfcvt_xu_f, vfwcvt_x_f, vfwcvt_xu_f, vfncvt_x_f, vfncvt_xu_f
vfcvt_f_x, vfcvt_f_xu, vfwcvt_f_x, vfwcvt_f_xu, vfwcvt_f_f, vfncvt_f_x
vfncvt_f_xu, vfncvt_f_f


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154635

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-costrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
  llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fround-costrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll