[PATCH] D154631: [RISCV] Add rounding mode control variant for vfmul, vfdiv, vfrdiv, vfwmul
Yueh-Ting (eop) Chen via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Jul 6 10:59:12 PDT 2023
eopXD created this revision.
eopXD added reviewers: craig.topper, reames, kito-cheng, rogfer01, frasercrmck.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson, qcolombet, MatzeB.
Herald added a project: All.
eopXD requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, wangpc, MaskRay.
Herald added projects: clang, LLVM.
Depends on D154629 <https://reviews.llvm.org/D154629>
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D154631
Files:
clang/include/clang/Basic/riscv_vector.td
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfdiv-out-of-range.c
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfmul-out-of-range.c
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfrdiv-out-of-range.c
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwmul-out-of-range.c
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
llvm/test/CodeGen/RISCV/rvv/vfdiv.ll
llvm/test/CodeGen/RISCV/rvv/vfmul.ll
llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll
llvm/test/CodeGen/RISCV/rvv/vfwmul.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
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