[clang] a8a6a49 - [RISCV] Use 'long' in sha512 builtin tests. NFC

[Craig Topper via cfe-commits]

Author: Craig Topper
Date: 2023-07-06T07:37:19-07:00
New Revision: a8a6a4947439766355fb7e3dd81947d7f54f687a

URL: https://github.com/llvm/llvm-project/commit/a8a6a4947439766355fb7e3dd81947d7f54f687a
DIFF: https://github.com/llvm/llvm-project/commit/a8a6a4947439766355fb7e3dd81947d7f54f687a.diff

LOG: [RISCV] Use 'long' in sha512 builtin tests. NFC

This matches the data type of the intrinsics. This case be seen
from the removal of sext and trunc instructions from the IR.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D154577

Added: 
    

Modified: 
    clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c

Removed: 
    


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diff  --git a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
index d04e09fea075a6..46cbe1867b440d 100644
--- a/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
+++ b/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
@@ -5,60 +5,52 @@
 
 // RV64ZKNH-LABEL: @sha512sig0(
 // RV64ZKNH-NEXT:  entry:
-// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
-// RV64ZKNH-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
-// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV64ZKNH-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
-// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sig0(i64 [[CONV]])
-// RV64ZKNH-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// RV64ZKNH-NEXT:    ret i32 [[CONV1]]
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKNH-NEXT:    store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sig0(i64 [[TMP0]])
+// RV64ZKNH-NEXT:    ret i64 [[TMP1]]
 //
-int sha512sig0(int rs1) {
+long sha512sig0(long rs1) {
   return __builtin_riscv_sha512sig0_64(rs1);
 }
 
 
 // RV64ZKNH-LABEL: @sha512sig1(
 // RV64ZKNH-NEXT:  entry:
-// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
-// RV64ZKNH-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
-// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV64ZKNH-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
-// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sig1(i64 [[CONV]])
-// RV64ZKNH-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// RV64ZKNH-NEXT:    ret i32 [[CONV1]]
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKNH-NEXT:    store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sig1(i64 [[TMP0]])
+// RV64ZKNH-NEXT:    ret i64 [[TMP1]]
 //
-int sha512sig1(int rs1) {
+long sha512sig1(long rs1) {
   return __builtin_riscv_sha512sig1_64(rs1);
 }
 
 
 // RV64ZKNH-LABEL: @sha512sum0(
 // RV64ZKNH-NEXT:  entry:
-// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
-// RV64ZKNH-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
-// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV64ZKNH-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
-// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sum0(i64 [[CONV]])
-// RV64ZKNH-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// RV64ZKNH-NEXT:    ret i32 [[CONV1]]
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKNH-NEXT:    store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sum0(i64 [[TMP0]])
+// RV64ZKNH-NEXT:    ret i64 [[TMP1]]
 //
-int sha512sum0(int rs1) {
+long sha512sum0(long rs1) {
   return __builtin_riscv_sha512sum0_64(rs1);
 }
 
 
 // RV64ZKNH-LABEL: @sha512sum1(
 // RV64ZKNH-NEXT:  entry:
-// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
-// RV64ZKNH-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
-// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
-// RV64ZKNH-NEXT:    [[CONV:%.*]] = sext i32 [[TMP0]] to i64
-// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sum1(i64 [[CONV]])
-// RV64ZKNH-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// RV64ZKNH-NEXT:    ret i32 [[CONV1]]
+// RV64ZKNH-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
+// RV64ZKNH-NEXT:    store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
+// RV64ZKNH-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sum1(i64 [[TMP0]])
+// RV64ZKNH-NEXT:    ret i64 [[TMP1]]
 //
-int sha512sum1(int rs1) {
+long sha512sum1(long rs1) {
   return __builtin_riscv_sha512sum1_64(rs1);
 }