[PATCH] D152623: [clang-format] Indent Verilog struct literal on new line
sstwcw via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Jun 29 08:39:27 PDT 2023
This revision was automatically updated to reflect the committed changes.
Closed by commit rG6bf66d839f13: [clang-format] Indent Verilog struct literal on new line (authored by sstwcw).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D152623/new/
https://reviews.llvm.org/D152623
Files:
clang/lib/Format/ContinuationIndenter.cpp
clang/unittests/Format/FormatTestVerilog.cpp
Index: clang/unittests/Format/FormatTestVerilog.cpp
===================================================================
--- clang/unittests/Format/FormatTestVerilog.cpp
+++ clang/unittests/Format/FormatTestVerilog.cpp
@@ -1172,6 +1172,15 @@
verifyFormat("c = '{a : 0, b : 0.0, default : 0};", Style);
verifyFormat("c = ab'{a : 0, b : 0.0};", Style);
verifyFormat("c = ab'{cd : cd'{1, 1.0}, ef : ef'{2, 2.0}};", Style);
+
+ // It should be indented correctly when the line has to break.
+ verifyFormat("c = //\n"
+ " '{default: 0};");
+ Style = getDefaultStyle();
+ Style.ContinuationIndentWidth = 2;
+ verifyFormat("c = //\n"
+ " '{default: 0};",
+ Style);
}
TEST_F(FormatTestVerilog, StructuredProcedure) {
Index: clang/lib/Format/ContinuationIndenter.cpp
===================================================================
--- clang/lib/Format/ContinuationIndenter.cpp
+++ clang/lib/Format/ContinuationIndenter.cpp
@@ -1173,7 +1173,15 @@
}
if (NextNonComment->is(TT_TemplateString) && NextNonComment->closesScope())
return State.Stack[State.Stack.size() - 2].LastSpace;
+ // Field labels in a nested type should be aligned to the brace. For example
+ // in ProtoBuf:
+ // optional int32 b = 2 [(foo_options) = {aaaaaaaaaaaaaaaaaaa: 123,
+ // bbbbbbbbbbbbbbbbbbbbbbbb:"baz"}];
+ // For Verilog, a quote following a brace is treated as an identifier. And
+ // Both braces and colons get annotated as TT_DictLiteral. So we have to
+ // check.
if (Current.is(tok::identifier) && Current.Next &&
+ (!Style.isVerilog() || Current.Next->is(tok::colon)) &&
(Current.Next->is(TT_DictLiteral) ||
((Style.Language == FormatStyle::LK_Proto ||
Style.Language == FormatStyle::LK_TextProto) &&
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