[PATCH] D154093: [clang-format] Break strings in Verilog

[sstwcw via Phabricator via cfe-commits]

sstwcw created this revision.
Herald added projects: All, clang, clang-format.
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Herald added reviewers: rymiel, HazardyKnusperkeks, owenpan, MyDeveloperDay.
sstwcw requested review of this revision.

In Verilog, concatenations need to have braces around them and commas
between the parts.

Some const qualifiers were removed.  It is because the new insertBreak
method modifies a field.  And adaptStartOfLine calls that method in
another class.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154093

Files:
  clang/docs/ClangFormatStyleOptions.rst
  clang/include/clang/Format/Format.h
  clang/lib/Format/BreakableToken.cpp
  clang/lib/Format/BreakableToken.h
  clang/lib/Format/ContinuationIndenter.cpp
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/lib/Format/WhitespaceManager.cpp
  clang/unittests/Format/FormatTestVerilog.cpp
  clang/unittests/Format/TokenAnnotatorTest.cpp

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