[PATCH] D151696: [x86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling

[Freddy, Ye via Phabricator via cfe-commits]

FreddyYe added a comment.

In D151696#4458435 <https://reviews.llvm.org/D151696#4458435>, @pengfei wrote:

> I have some concerns for RULE 3, especially `core_aes_pclmulqdq -> westmere` and `atom_sse4_2_movbe -> silvermont`.
> Sometimes, we have minor feature differences in the same generation targets. I guess that's why we use `arch_feature` naming like core_2_duo_ssse3. Merging them into the same generation or the next generation might corrup the intention here. But I'm not expert in CPUDispatch, and I don't see any existing tests for them, so I won't block the patch since it's an improvement in general.
> Please wait a few days for other reviewers' opinions.

You are right. For historical reasons, I can't find which product each cpu name string points to actually. From the old feature list in X86TargetParser.def, these three cpu names even share a same feature list:

  atom_sse4_2
  core_i7_sse4_2
  core_aes_pclmulqdq

"core_5th_gen_avx_tsx"  is also same as "broadwell". So I have a new proposal for RULE3, which can be considered to be more conservative:

  pentium_4_sse3 -> prescott (FeatureSSE3)
      First introduce FeatureSSE4_1 like prescott
  core_2_duo_ssse3 -> core2 (FeatureSSSE3)
      First introduce FeatureSSE4_1 like core2
  core_2_duo_sse4_1 -> penryn (FeatureSSE4_1)
      First introduce FeatureSSE4_1 like penryn
  atom_sse4_2 -> nehalem (FeatureSSE4_2)
      First introduce FeatureSSE4_2 like nehalem
  core_i7_sse4_2 -> nehalem (FeatureSSE4_2)
      First introduce FeatureSSE4_2 like nehalem
  core_aes_pclmulqdq -> nehalem (FeatureSSE4_2)
      First introduce FeatureSSE4_2 like nehalem
  core_5th_gen_avx_tsx -> broadwell 
      Same feature list as broadwell

Meanwhile, the fact above won't affect code changes in X86.td. I'll still define these new cpu names with the TUNE_NAME info in original source.


Repository:
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https://reviews.llvm.org/D151696