[PATCH] D153659: [RISCV] Fix name mangling for LMUL!=1 vector types with attribute(rvv_vector_bits)

[Craig Topper via Phabricator via cfe-commits]

craig.topper created this revision.
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We were always printing "m1", we need to calculate the correct LMUL instead.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153659

Files:
  clang/lib/AST/ItaniumMangle.cpp
  clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
  clang/test/CodeGenCXX/riscv-rvv-fixedtypeinfo.cpp

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