[PATCH] D152623: [clang-format] Indent Verilog struct literal on new line

[sstwcw via Phabricator via cfe-commits]

sstwcw added a comment.

> So I assume your `'` is a 'DictLiteral`?

The brace following the quote is a `DictLiteral`.  The quote is a `tok::identifier` and `TT_Unknown`.

> Does it have to be one?

The brace is set to this type when used this way in all other languages.  I don't want to make an exception.

> I don't know what else maybe a `DictLiteral` in what language and am not so comfortable with this change.

I changed the patch to use the new behavior only for Verilog.

The `DictLiteral` type gets set on the braces and colons in literals where the field names and values are separated by colons in all languages that have them.  In addition, because the protocol buffer text format allows angular brackets as braces, the type is also set on those angular brackets for that language.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D152623/new/

https://reviews.llvm.org/D152623