[PATCH] D152623: [clang-format] Indent Verilog struct literal on new line

[Björn Schäpers via Phabricator via cfe-commits]

HazardyKnusperkeks added a comment.

So I assume your `'` is a 'DictLiteral`? Does it have to be one? I don't know what else maybe a `DictLiteral` in what language and am not so comfortable with this change.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152623/new/

https://reviews.llvm.org/D152623