Author: Paulo Matos
Date: 2023-06-06T07:48:35+02:00
New Revision: 9571a28ee4e801a7796569d62fe037fc22cd65a4
URL: https://github.com/llvm/llvm-project/commit/9571a28ee4e801a7796569d62fe037fc22cd65a4
DIFF: https://github.com/llvm/llvm-project/commit/9571a28ee4e801a7796569d62fe037fc22cd65a4.diff
LOG: [WebAssembly] Add tests ensuring rotates persist
Due to the nature of WebAssembly, it's always better to keep
rotates instead of trying to optimize it. Commit 9485d983
disabled the generation of fsh for rotates, however these
tests ensure that future changes don't change the behaviour for
the Wasm backend that tends to have different optimization
requirements than other architectures. Also see:
https://github.com/llvm/llvm-project/issues/62703
Differential Revision: https://reviews.llvm.org/D152126
Added:
clang/test/CodeGen/WebAssembly/wasm-rotate.c
llvm/test/CodeGen/WebAssembly/rotate-i3264.ll
Modified:
Removed:
################################################################################
diff --git a/clang/test/CodeGen/WebAssembly/wasm-rotate.c b/clang/test/CodeGen/WebAssembly/wasm-rotate.c
new file mode 100644
index 0000000000000..a9579d6bdb366
--- /dev/null
+++ b/clang/test/CodeGen/WebAssembly/wasm-rotate.c
@@ -0,0 +1,53 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// RUN: %clang_cc1 -triple wasm32-unknown-unknown -o - -emit-llvm %s | FileCheck --check-prefix=WEBASSEMBLY32 %s
+// RUN: %clang_cc1 -triple wasm64-unknown-unknown -o - -emit-llvm %s | FileCheck --check-prefix=WEBASSEMBLY64 %s
+
+// WEBASSEMBLY32-LABEL: define i32 @test32
+// WEBASSEMBLY32-SAME: (i32 noundef [[X:%.*]]) #[[ATTR0:[0-9]+]] {
+// WEBASSEMBLY32-NEXT: entry:
+// WEBASSEMBLY32-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
+// WEBASSEMBLY32-NEXT: store i32 [[X]], ptr [[X_ADDR]], align 4
+// WEBASSEMBLY32-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
+// WEBASSEMBLY32-NEXT: [[AND:%.*]] = and i32 [[TMP0]], -16711936
+// WEBASSEMBLY32-NEXT: [[TMP1:%.*]] = call i32 @llvm.fshl.i32(i32 [[AND]], i32 [[AND]], i32 8)
+// WEBASSEMBLY32-NEXT: ret i32 [[TMP1]]
+//
+// WEBASSEMBLY64-LABEL: define i32 @test32
+// WEBASSEMBLY64-SAME: (i32 noundef [[X:%.*]]) #[[ATTR0:[0-9]+]] {
+// WEBASSEMBLY64-NEXT: entry:
+// WEBASSEMBLY64-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
+// WEBASSEMBLY64-NEXT: store i32 [[X]], ptr [[X_ADDR]], align 4
+// WEBASSEMBLY64-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
+// WEBASSEMBLY64-NEXT: [[AND:%.*]] = and i32 [[TMP0]], -16711936
+// WEBASSEMBLY64-NEXT: [[TMP1:%.*]] = call i32 @llvm.fshl.i32(i32 [[AND]], i32 [[AND]], i32 8)
+// WEBASSEMBLY64-NEXT: ret i32 [[TMP1]]
+//
+unsigned int test32(unsigned int x) {
+ return __builtin_rotateleft32((x & 0xFF00FF00), 8);
+}
+
+// WEBASSEMBLY32-LABEL: define i32 @test64
+// WEBASSEMBLY32-SAME: (i32 noundef [[X:%.*]]) #[[ATTR0]] {
+// WEBASSEMBLY32-NEXT: entry:
+// WEBASSEMBLY32-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
+// WEBASSEMBLY32-NEXT: store i32 [[X]], ptr [[X_ADDR]], align 4
+// WEBASSEMBLY32-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
+// WEBASSEMBLY32-NEXT: [[CONV:%.*]] = zext i32 [[TMP0]] to i64
+// WEBASSEMBLY32-NEXT: [[AND:%.*]] = and i64 [[CONV]], -71777214294589696
+// WEBASSEMBLY32-NEXT: [[TMP1:%.*]] = call i64 @llvm.fshl.i64(i64 [[AND]], i64 [[AND]], i64 8)
+// WEBASSEMBLY32-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
+// WEBASSEMBLY32-NEXT: ret i32 [[CONV1]]
+//
+// WEBASSEMBLY64-LABEL: define i64 @test64
+// WEBASSEMBLY64-SAME: (i64 noundef [[X:%.*]]) #[[ATTR0]] {
+// WEBASSEMBLY64-NEXT: entry:
+// WEBASSEMBLY64-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8
+// WEBASSEMBLY64-NEXT: store i64 [[X]], ptr [[X_ADDR]], align 8
+// WEBASSEMBLY64-NEXT: [[TMP0:%.*]] = load i64, ptr [[X_ADDR]], align 8
+// WEBASSEMBLY64-NEXT: [[AND:%.*]] = and i64 [[TMP0]], -71777214294589696
+// WEBASSEMBLY64-NEXT: [[TMP1:%.*]] = call i64 @llvm.fshl.i64(i64 [[AND]], i64 [[AND]], i64 8)
+// WEBASSEMBLY64-NEXT: ret i64 [[TMP1]]
+//
+unsigned long test64(unsigned long x) {
+ return __builtin_rotateleft64((x & 0xFF00FF00FF00FF00L), 8);
+}
diff --git a/llvm/test/CodeGen/WebAssembly/rotate-i3264.ll b/llvm/test/CodeGen/WebAssembly/rotate-i3264.ll
new file mode 100644
index 0000000000000..209f0e43be722
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/rotate-i3264.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: sed 's/iX/i32/g' %s | llc --mtriple=wasm32-unknown-unknown | FileCheck --check-prefix=I32 %s
+; RUN: sed 's/iX/i64/g' %s | llc --mtriple=wasm64-unknown-unknown | FileCheck --check-prefix=I64 %s
+
+declare iX @llvm.fshl.iX(iX, iX, iX)
+declare iX @llvm.fshr.iX(iX, iX, iX)
+
+; from https://github.com/llvm/llvm-project/issues/62703
+
+define iX @testLeft(iX noundef %0, iX noundef %1) {
+; I32-LABEL: testLeft:
+; I32: .functype testLeft (i32, i32) -> (i32)
+; I32-NEXT: # %bb.0:
+; I32-NEXT: local.get 0
+; I32-NEXT: local.get 1
+; I32-NEXT: i32.rotl
+; I32-NEXT: # fallthrough-return
+;
+; I64-LABEL: testLeft:
+; I64: .functype testLeft (i64, i64) -> (i64)
+; I64-NEXT: # %bb.0:
+; I64-NEXT: local.get 0
+; I64-NEXT: local.get 1
+; I64-NEXT: i64.rotl
+; I64-NEXT: # fallthrough-return
+ %3 = call iX @llvm.fshl.iX(iX %0, iX %0, iX %1)
+ ret iX %3
+}
+
+define iX @testRight(iX noundef %0, iX noundef %1) {
+; I32-LABEL: testRight:
+; I32: .functype testRight (i32, i32) -> (i32)
+; I32-NEXT: # %bb.0:
+; I32-NEXT: local.get 0
+; I32-NEXT: local.get 1
+; I32-NEXT: i32.rotr
+; I32-NEXT: # fallthrough-return
+;
+; I64-LABEL: testRight:
+; I64: .functype testRight (i64, i64) -> (i64)
+; I64-NEXT: # %bb.0:
+; I64-NEXT: local.get 0
+; I64-NEXT: local.get 1
+; I64-NEXT: i64.rotr
+; I64-NEXT: # fallthrough-return
+ %3 = call iX @llvm.fshr.iX(iX %0, iX %0, iX %1)
+ ret iX %3
+}