[PATCH] D151601: [NVPTX] Coalesce register classes for {i16,f16,bf16}, {i32,v2f16,v2bf16}

[Artem Belevich via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGdc90f42ea7b4: Coalesce 16-bit FP types to use integer register classes. (authored by tra).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151601/new/

https://reviews.llvm.org/D151601

Files:
  clang/test/CodeGenCUDA/bf16.cu
  llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
  llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
  llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
  llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
  llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
  llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
  llvm/lib/Target/NVPTX/NVPTXProxyRegErasure.cpp
  llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
  llvm/lib/Target/NVPTX/NVPTXRegisterInfo.td
  llvm/test/CodeGen/NVPTX/bf16.ll
  llvm/test/CodeGen/NVPTX/call_bitcast_byval.ll
  llvm/test/CodeGen/NVPTX/f16-instructions.ll
  llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
  llvm/test/CodeGen/NVPTX/half.ll
  llvm/test/CodeGen/NVPTX/intrinsics-sm90.ll
  llvm/test/CodeGen/NVPTX/ld-st-addrrspace.py
  llvm/test/CodeGen/NVPTX/ldg-invariant.ll
  llvm/test/CodeGen/NVPTX/ldu-ldg.ll
  llvm/test/CodeGen/NVPTX/param-load-store.ll
  llvm/test/CodeGen/NVPTX/proxy-reg-erasure-ptx.ll
  llvm/test/CodeGen/NVPTX/wmma.py

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