[clang] 24231df - [clang-format] Parse the Verilog language option in configuration

[via cfe-commits]

Author: sstwcw
Date: 2023-06-02T14:59:27Z
New Revision: 24231df9b8ef560cc6d3c713d5dba1de703e2cb9

URL: https://github.com/llvm/llvm-project/commit/24231df9b8ef560cc6d3c713d5dba1de703e2cb9
DIFF: https://github.com/llvm/llvm-project/commit/24231df9b8ef560cc6d3c713d5dba1de703e2cb9.diff

LOG: [clang-format] Parse the Verilog language option in configuration

Reviewed By: HazardyKnusperkeks, MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D151632

Added: 
    

Modified: 
    clang/lib/Format/Format.cpp
    clang/unittests/Format/ConfigParseTest.cpp

Removed: 
    


################################################################################
diff  --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp
index d7128ed558dc5..6e2b6a662e7e1 100644
--- a/clang/lib/Format/Format.cpp
+++ b/clang/lib/Format/Format.cpp
@@ -375,6 +375,7 @@ template <> struct ScalarEnumerationTraits<FormatStyle::LanguageKind> {
     IO.enumCase(Value, "TextProto", FormatStyle::LK_TextProto);
     IO.enumCase(Value, "CSharp", FormatStyle::LK_CSharp);
     IO.enumCase(Value, "Json", FormatStyle::LK_Json);
+    IO.enumCase(Value, "Verilog", FormatStyle::LK_Verilog);
   }
 };
 

diff  --git a/clang/unittests/Format/ConfigParseTest.cpp b/clang/unittests/Format/ConfigParseTest.cpp
index 0e47abed12472..169c93d1143eb 100644
--- a/clang/unittests/Format/ConfigParseTest.cpp
+++ b/clang/unittests/Format/ConfigParseTest.cpp
@@ -1022,6 +1022,23 @@ TEST(ConfigParseTest, ParsesConfigurationWithLanguages) {
             ParseError::Error);
 
   EXPECT_EQ(FormatStyle::LK_Cpp, Style.Language);
+
+  Style.Language = FormatStyle::LK_Verilog;
+  CHECK_PARSE("---\n"
+              "Language: Verilog\n"
+              "IndentWidth: 12\n"
+              "---\n"
+              "Language: Cpp\n"
+              "IndentWidth: 34\n"
+              "...\n",
+              IndentWidth, 12u);
+  CHECK_PARSE("---\n"
+              "IndentWidth: 78\n"
+              "---\n"
+              "Language: Verilog\n"
+              "IndentWidth: 56\n"
+              "...\n",
+              IndentWidth, 56u);
 }
 
 TEST(ConfigParseTest, UsesLanguageForBasedOnStyle) {