[PATCH] D151863: [x86][MC] Fix movdir64b addressing
Akshay Khadse via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Fri Jun 2 00:11:32 PDT 2023
akshaykhadse updated this revision to Diff 527764.
akshaykhadse added a comment.
Address review comments
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D151863/new/
https://reviews.llvm.org/D151863
Files:
clang/test/CodeGen/ms-inline-asm-64.c
clang/test/CodeGen/ms-inline-asm.c
llvm/lib/Target/X86/AsmParser/X86Operand.h
llvm/test/MC/X86/x86-64-movdir64b-intel.s
Index: llvm/test/MC/X86/x86-64-movdir64b-intel.s
===================================================================
--- /dev/null
+++ llvm/test/MC/X86/x86-64-movdir64b-intel.s
@@ -0,0 +1,4 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// CHECK: movdir64b rax, zmmword ptr [rax - 4096]
+// CHECK: encoding: [0x66,0x0f,0x38,0xf8,0x80,0x00,0xf0,0xff,0xff]
+ movdir64b rax, zmmword ptr [rax - 4096]
Index: llvm/lib/Target/X86/AsmParser/X86Operand.h
===================================================================
--- llvm/lib/Target/X86/AsmParser/X86Operand.h
+++ llvm/lib/Target/X86/AsmParser/X86Operand.h
@@ -383,6 +383,9 @@
bool isMem512_GR16() const {
if (!isMem512())
return false;
+ if (getMemBaseReg() == X86::AH) {
+ return true;
+ }
if (getMemBaseReg() &&
!X86MCRegisterClasses[X86::GR16RegClassID].contains(getMemBaseReg()))
return false;
@@ -391,27 +394,33 @@
bool isMem512_GR32() const {
if (!isMem512())
return false;
- if (getMemBaseReg() &&
- !X86MCRegisterClasses[X86::GR32RegClassID].contains(getMemBaseReg()) &&
- getMemBaseReg() != X86::EIP)
- return false;
if (getMemIndexReg() &&
!X86MCRegisterClasses[X86::GR32RegClassID].contains(getMemIndexReg()) &&
getMemIndexReg() != X86::EIZ)
return false;
+ if (getMemBaseReg() == X86::AH) {
+ return true;
+ }
+ if (getMemBaseReg() &&
+ !X86MCRegisterClasses[X86::GR32RegClassID].contains(getMemBaseReg()) &&
+ getMemBaseReg() != X86::EIP)
+ return false;
return true;
}
bool isMem512_GR64() const {
if (!isMem512())
return false;
- if (getMemBaseReg() &&
- !X86MCRegisterClasses[X86::GR64RegClassID].contains(getMemBaseReg()) &&
- getMemBaseReg() != X86::RIP)
- return false;
if (getMemIndexReg() &&
!X86MCRegisterClasses[X86::GR64RegClassID].contains(getMemIndexReg()) &&
getMemIndexReg() != X86::RIZ)
return false;
+ if (getMemBaseReg() == X86::AH) {
+ return true;
+ }
+ if (getMemBaseReg() &&
+ !X86MCRegisterClasses[X86::GR64RegClassID].contains(getMemBaseReg()) &&
+ getMemBaseReg() != X86::RIP)
+ return false;
return true;
}
Index: clang/test/CodeGen/ms-inline-asm.c
===================================================================
--- clang/test/CodeGen/ms-inline-asm.c
+++ clang/test/CodeGen/ms-inline-asm.c
@@ -675,6 +675,13 @@
// CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", "~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
}
+void t47(void) {
+ // CHECK-LABEL: define{{.*}} void @t47
+ int arr[1000];
+ __asm movdir64b eax, zmmword ptr [arr]
+ // CHECK: call void asm sideeffect inteldialect "movdir64b eax, zmmword ptr $0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}
+
void dot_operator(void){
// CHECK-LABEL: define{{.*}} void @dot_operator
__asm { mov eax, 3[ebx]A.b}
Index: clang/test/CodeGen/ms-inline-asm-64.c
===================================================================
--- clang/test/CodeGen/ms-inline-asm-64.c
+++ clang/test/CodeGen/ms-inline-asm-64.c
@@ -72,3 +72,10 @@
// CHECK-SAME: jmp ${1:P}
// CHECK-SAME: "*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(void (...)) @bar, ptr elementtype(void (...)) @bar)
}
+
+void t47(void) {
+ // CHECK-LABEL: define{{.*}} void @t47
+ int arr[1000];
+ __asm movdir64b rax, zmmword ptr [arr]
+ // CHECK: call void asm sideeffect inteldialect "movdir64b rax, zmmword ptr $0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}
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