[PATCH] D151601: Coalesce register classes for {i16,f16,bf16}, {i32,v2f16,v2bf16}

[Artem Belevich via Phabricator via cfe-commits]

tra created this revision.
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tra updated this revision to Diff 526756.
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tra updated this revision to Diff 527245.
tra updated this revision to Diff 527609.
tra retitled this revision from "Coalesce i16/f16/bf16 to use the same register class." to "Coalesce register classes for {i16,f16,bf16}, {i32,v2f16,v2bf16}".
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Switched v2f16 and v2bf16 to use the same registers as i32.


tra added a comment.

Removed now-redundant LD/ST instructions for f16/bf16/v2f16/v2bf16


tra added a comment.

Removed more unnecessary stuff and reduced unnecessary register copying.


They all use the same 16/32 bit PTX registers and there's no point creating more register classes for each.

The changes are largely mechanical replacing *f16 register classes with i16/i32, with the exception of a minor optimization to the register copying. We now produce smaller number of pointless register moves.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151601

Files:
  clang/test/CodeGenCUDA/bf16.cu
  llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
  llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
  llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
  llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
  llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
  llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
  llvm/lib/Target/NVPTX/NVPTXProxyRegErasure.cpp
  llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
  llvm/lib/Target/NVPTX/NVPTXRegisterInfo.td
  llvm/test/CodeGen/NVPTX/bf16.ll
  llvm/test/CodeGen/NVPTX/call_bitcast_byval.ll
  llvm/test/CodeGen/NVPTX/f16-instructions.ll
  llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
  llvm/test/CodeGen/NVPTX/half.ll
  llvm/test/CodeGen/NVPTX/intrinsics-sm90.ll
  llvm/test/CodeGen/NVPTX/ld-st-addrrspace.py
  llvm/test/CodeGen/NVPTX/ldg-invariant.ll
  llvm/test/CodeGen/NVPTX/ldu-ldg.ll
  llvm/test/CodeGen/NVPTX/param-load-store.ll
  llvm/test/CodeGen/NVPTX/proxy-reg-erasure-ptx.ll
  llvm/test/CodeGen/NVPTX/wmma.py

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