[PATCH] D151869: [RISCV] Support more builtin for zvfhmin.

[Jianjian Guan via Phabricator via cfe-commits]

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This patch enables some fp16 vector type builtins that don't use fp arithmetic instruction for zvfhmin.
Include following builtins:

  vector load/store,
  vector reinterpret,
  vmerge_vvm,
  vmv_v.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151869

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c

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