[PATCH] D151867: [Clang][RISCV] Make generic clz/ctz builtins defined for zero on RISCV targets.

[Yunze Zhu(Thead) via Phabricator via cfe-commits]

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For now llvm intrinsic ctlz/cttz are supported by extension zbb and xtheadbb,
and both extensions support returning well-defined results for zero inputs.
It's possible to set isCLZForZeroUndef flag to false by default on RISCV targets
as ARM and other target does.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151867

Files:
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c

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