[clang] a5e5eea - Revert "[RISCV] Add Zvfhmin extension for clang."
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Wed May 31 10:17:55 PDT 2023
Author: Craig Topper
Date: 2023-05-31T10:17:11-07:00
New Revision: a5e5eea29ca9e5b5d191b0316ecd8434a6c5afe1
URL: https://github.com/llvm/llvm-project/commit/a5e5eea29ca9e5b5d191b0316ecd8434a6c5afe1
DIFF: https://github.com/llvm/llvm-project/commit/a5e5eea29ca9e5b5d191b0316ecd8434a6c5afe1.diff
LOG: Revert "[RISCV] Add Zvfhmin extension for clang."
This reverts commit 35a0079238ce9fc36cdc8c6a2895eb5538bf7b4a.
The backend support is not present yet. The intrinsics will crash
the compiler if compiled to assembly or binary.
Added:
Modified:
clang/include/clang/Basic/riscv_vector.td
clang/include/clang/Support/RISCVVIntrinsicUtils.h
clang/lib/Sema/Sema.cpp
clang/lib/Sema/SemaRISCVVectorLookup.cpp
clang/test/Sema/riscv-vector-float16-check.c
clang/utils/TableGen/RISCVVEmitter.cpp
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
Removed:
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
################################################################################
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 35b1536f72d3b..4d48c38adb578 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2215,13 +2215,7 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">;
def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "csi", "vfwcvt_f">;
def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">;
- def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "f", "vfwcvt_f">;
- let RequiredFeatures = ["ZvfhminOrZvfh"] in
- def vfwcvt_f_f_v_fp16 : RVVConvBuiltin<"w", "wv", "x", "vfwcvt_f"> {
- let Name = "vfwcvt_f_f_v";
- let IRName = "vfwcvt_f_f_v";
- let MaskedIRName = "vfwcvt_f_f_v_mask";
- }
+ def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "xf", "vfwcvt_f">;
}
// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
@@ -2232,13 +2226,7 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_f_xu_w : RVVConvBuiltin<"Fv", "FvUw", "csi", "vfncvt_f">;
def vfncvt_f_x_w : RVVConvBuiltin<"Fv", "Fvw", "csi", "vfncvt_f">;
- def vfncvt_f_f_w : RVVConvBuiltin<"v", "vw", "f", "vfncvt_f">;
- let RequiredFeatures = ["ZvfhminOrZvfh"] in
- def vfncvt_f_f_w_fp16 : RVVConvBuiltin<"v", "vw", "x", "vfncvt_f"> {
- let Name = "vfncvt_f_f_w";
- let IRName = "vfncvt_f_f_w";
- let MaskedIRName = "vfncvt_f_f_w_mask";
- }
+ def vfncvt_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_f">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
}
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 7f2b5d9c28c48..2a81e7972358e 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -470,8 +470,7 @@ enum RVVRequire : uint8_t {
RVV_REQ_None = 0,
RVV_REQ_RV64 = 1 << 0,
RVV_REQ_FullMultiply = 1 << 1,
- RVV_REQ_ZvfhminOrZvfh = 1 << 2,
- RVV_REQ_Xsfvcp = 1 << 3,
+ RVV_REQ_Xsfvcp = 1 << 2,
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Xsfvcp)
};
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index c4349c7a6fb50..532fb834bcf4f 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2044,10 +2044,9 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) {
!TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zve64x";
if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ true) &&
- !TI.hasFeature("experimental-zvfh") &&
- !TI.hasFeature("experimental-zvfhmin"))
+ !TI.hasFeature("experimental-zvfh"))
Diag(Loc, diag::err_riscv_type_requires_extension, FD)
- << Ty << "zvfh or zvfhmin";
+ << Ty << "zvfh";
if (Ty->isRVVType(/* Bitwidth */ 32, /* IsFloat */ true) &&
!TI.hasFeature("zve32f"))
Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zve32f";
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index be955a139c641..5599b9277cd79 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -195,8 +195,6 @@ void RISCVIntrinsicManagerImpl::InitIntrinsicList() {
const TargetInfo &TI = Context.getTargetInfo();
bool HasRV64 = TI.hasFeature("64bit");
bool HasFullMultiply = TI.hasFeature("v");
- bool HasZvfh = TI.hasFeature("experimental-zvfh");
- bool HasZvfhminOrZvfh = TI.hasFeature("experimental-zvfhmin") || HasZvfh;
auto ConstructRVVIntrinsics = [&](ArrayRef<RVVIntrinsicRecord> Recs,
IntrinsicKind K) {
@@ -259,16 +257,6 @@ void RISCVIntrinsicManagerImpl::InitIntrinsicList() {
!HasFullMultiply)
continue;
- if (BaseType == BasicType::Float16) {
- if ((Record.RequiredExtensions & RVV_REQ_ZvfhminOrZvfh) ==
- RVV_REQ_ZvfhminOrZvfh) {
- if (!HasZvfhminOrZvfh)
- continue;
- } else if (!HasZvfh) {
- continue;
- }
- }
-
// Expanded with
diff erent LMUL.
for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {
if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3))))
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
deleted file mode 100644
index bd96a3d66457f..0000000000000
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
+++ /dev/null
@@ -1,24 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
-// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
-// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
-// RUN: FileCheck --check-prefix=CHECK-ZVF %s
-
-// RUN: not %clang_cc1 -triple riscv64 -target-feature +v \
-// RUN: -target-feature +experimental-zvfhmin -emit-llvm-only %s 2>&1 | \
-// RUN: FileCheck %s --check-prefix=CHECK-ZVFHMIN-ERR
-
-#include <riscv_vector.h>
-
-// CHECK-ZVF-LABEL: @test_vfadd_vv_f16m1(
-// CHECK-ZVF-NEXT: entry:
-// CHECK-ZVF-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 [[VL:%.*]])
-// CHECK-ZVF-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-
-// CHECK-ZVFHMIN-ERR: no matching function for call to '__riscv_vfadd'
-
-vfloat16m1_t test_vfadd_vv_f16m1(vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
- return __riscv_vfadd(op1, op2, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
deleted file mode 100644
index c000d859a5639..0000000000000
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
+++ /dev/null
@@ -1,27 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
-// RUN: -target-feature +experimental-zvfhmin -disable-O0-optnone \
-// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
-// RUN: FileCheck --check-prefix=CHECK-ZVFHMIN %s
-
-#include <riscv_vector.h>
-
-// CHECK-ZVFHMIN-LABEL: @test_vfncvt_f_f_w_f16m1(
-// CHECK-ZVFHMIN-NEXT: entry:
-// CHECK-ZVFHMIN-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
-// CHECK-ZVFHMIN-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
- return __riscv_vfncvt_f(src, vl);
-}
-
-
-// CHECK-ZVFHMIN-LABEL: @test_vfwcvt_f_f_v_f16m1(
-// CHECK-ZVFHMIN-NEXT: entry:
-// CHECK-ZVFHMIN-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
-// CHECK-ZVFHMIN-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vfwcvt_f_f_v_f16m1(vfloat16m1_t src, size_t vl) {
- return __riscv_vfwcvt_f(src, vl);
-}
diff --git a/clang/test/Sema/riscv-vector-float16-check.c b/clang/test/Sema/riscv-vector-float16-check.c
index 57e087ba68ec4..48959254d2ad4 100644
--- a/clang/test/Sema/riscv-vector-float16-check.c
+++ b/clang/test/Sema/riscv-vector-float16-check.c
@@ -4,5 +4,5 @@
// REQUIRES: riscv-registered-target
#include <riscv_vector.h>
-vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
+vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
} /* expected-warning {{non-void function does not return a value}}*/
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp
index cc64b5e4d8aa1..35b2203cecf34 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -633,7 +633,6 @@ void RVVEmitter::createRVVIntrinsics(
RVVRequire RequireExt = StringSwitch<RVVRequire>(RequiredFeature)
.Case("RV64", RVV_REQ_RV64)
.Case("FullMultiply", RVV_REQ_FullMultiply)
- .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
.Case("Xsfvcp", RVV_REQ_Xsfvcp)
.Default(RVV_REQ_None);
assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 444cf14d8fcb0..c5b42840b6881 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -152,7 +152,6 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zvfbfmin", RISCVExtensionVersion{0, 6}},
{"zvfbfwma", RISCVExtensionVersion{0, 6}},
{"zvfh", RISCVExtensionVersion{0, 1}},
- {"zvfhmin", RISCVExtensionVersion{0, 1}},
{"ztso", RISCVExtensionVersion{0, 1}},
// vector crypto
@@ -944,7 +943,6 @@ static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
static const char *ImpliedExtsZvfbfmin[] = {"zve32f"};
static const char *ImpliedExtsZvfbfwma[] = {"zve32f"};
static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"};
-static const char *ImpliedExtsZvfhmin[] = {"zve32f"};
static const char *ImpliedExtsZvkn[] = {"zvbb", "zvbc", "zvkned", "zvknhb",
"zvkt"};
static const char *ImpliedExtsZvkng[] = {"zvkg", "zvkn"};
@@ -1006,7 +1004,6 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
{{"zvfbfmin"}, {ImpliedExtsZvfbfmin}},
{{"zvfbfwma"}, {ImpliedExtsZvfbfwma}},
{{"zvfh"}, {ImpliedExtsZvfh}},
- {{"zvfhmin"}, {ImpliedExtsZvfhmin}},
{{"zvkn"}, {ImpliedExtsZvkn}},
{{"zvkng"}, {ImpliedExtsZvkng}},
{{"zvknhb"}, {ImpliedExtsZvknhb}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index c7ce850529af0..d5213a07ea1ca 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -472,11 +472,6 @@ def FeatureStdExtZvfh
"'Zvfh' (Vector Half-Precision Floating-Point)",
[FeatureStdExtZve32f, FeatureStdExtZfhmin]>;
-def FeatureStdExtZvfhmin
- : SubtargetFeature<"experimental-zvfhmin", "HasStdExtZvfhmin", "true",
- "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
- [FeatureStdExtZve32f]>;
-
def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
def HasStdExtZfhOrZvfh
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